CEG 2136 LAB 3 Arithmetic Logic Unit

Java Python CEG 2136 Lab 3

LAB 3 Arithmetic Logic Unit

1.   Purpose:

In this lab students will design, simulate, build and test an Arithmetic Logic Unit (ALU),  employing Quartus II as a development environment and the Altera DE2-115 board as  experimental platform. ALU has to execute 16 different operations on two operands of 4  bits and will provide a 4-bit result along with 4 status bits (oVerflow, Zero, Negative,  Carry). The input operands will be generated by slide switches (or by “input_generator” component if you are testing your design remotely), while the result and the status bits will  be displayed on LEDs.

2.   Requirements of the Lab:

The following will be submitted in your report.

* Functional and truth tables, equations and schematics of your design

* Log of what you did

* Screen shots of all schematics and waveform. diagrams

* Compilation, simulation and downloading messages (if any)

* Test results

3.   Equipment and Supplies:

* Quartus II (student edition or web edition)

* Altera DE2-115 board with USB-Blaster cable and Power supply 12 VDC, 2A

4.   References:

4.1. Chapter1 - 4 of the Textbook: Computer System Architecture, Morris Mano, 3rd Ed.

4.2.  Course notes and

4.3. DE2-115 User Manual posted  in  the Documentation section  under  the Laboratories tab of CEG2136 Virtual Campus.

5. PreLab - Design of the ALU

5.1. ALU structure

The Central Processing Unit (CPU) consists of a Control Unit (CU) and a Datapath (execution unit – EU) as shown in the block diagram of Figure 1.

The CPU’s datapath contains registers to store data (A, B, C) and control (S) / status (V,Z,N,Cy) information, along an Arithmetic and Logic Unit (ALU). You have to design CPU’s datapath that can pe