ARM指令寻址模式，内存访问3种格式

ARM指令的三种寻址模式：
1）基址偏移

LDR R1，[R2,#-0x10]

2）基址偏移前变址

LDR R1，[R2,#-0x10]！ // R1 =*(R2-0x10),R2=R2-0x10

3）基址偏移后变址

LDR R1，[R2],#-0x10 // R1 =*(R2),R2=R2-0x10;

A8.5 Memory accesses
Commonly, the following addressing modes are permitted for memory access instructions:
Offset addressing
The offset value is applied to an address obtained from the base register. The result is used as the
address for the memory access. The value of the base register is unchanged.
The assembly language syntax for this mode is:
[, ]
Pre-indexed addressing
The offset value is applied to an address obtained from the base register. The result is used as the
address for the memory access, and written back into the base register.
The assembly language syntax for this mode is:
[, ]!
Post-indexed addressing
The address obtained from the base register is used, unchanged, as the address for the memory
access. The offset value is applied to the address, and written back into the base register
The assembly language syntax for this mode is:
[],
In each case, is the base register. can be:
? an immediate constant, such as or
? an index register,
? a shifted index register, such as , LSL #.

See ：ARM® Architecture Reference Manual
ARMv7-A and ARMv7-R edition

A8.8.60 LDMDB/LDMEA
Load Multiple Decrement Before (Load Multiple Empty Ascending) loads multiple registers from consecutive
memory locations using an address from a base register. The consecutive memory locations end just below this
address, and the address of the lowest of those locations can optionally be written back to the base register. The
registers loaded can include the PC, causing a branch to a loaded address.
Related system instructions are LDM (User registers) on page B9-1988 and LDM (exception return) on
page B9-1986.
n = UInt(Rn); registers = P:M:’0’:register_list; wback = (W == ‘1’);
if n == 15 || BitCount(registers) < 2 || (P == ‘1’ && M == ‘1’) then UNPREDICTABLE;
if registers<15> == ‘1’ && InITBlock() && !LastInITBlock() then UNPREDICTABLE;
if wback && registers == ‘1’ then UNPREDICTABLE;
For the case when cond is 0b1111, see Unconditional instructions on page A5-216.
n = UInt(Rn); registers = register_list; wback = (W == ‘1’);
if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE;
if wback && registers == ‘1’ && ArchVersion() >= 7 then UNPREDICTABLE;
Encoding T1 ARMv6T2, ARMv7
LDMDB {!},
Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
LDMDB {!},
1 1 0 1 0 0 1 0 0 W 1 Rn P M (0) register_list
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1
1514131211 10 9 8 7 6 5 4 3 2 1 0
cond 1 0 0 1 0 0 W 1 Rn register_list
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
A8 Instruction Descriptions
A8.8 Alphabetical list of instructions
ARM DDI 0406C.c Copyright © 1996-1998, 2000, 2004-2012, 2014 ARM. All rights reserved. A8-403
ID051414 Non-Confidential
Assembler syntax
LDMDB{}{} {!},
where:
, See Standard assembler syntax fields on page A8-287.
The base register. The SP can be used.
! Causes the instruction to write a modified value back to . Encoded as W = 1.
If ! is omitted, the instruction does not change in this way. Encoded as W = 0.
Is a list of one or more registers to be loaded, separated by commas and surrounded by { and }. The
lowest-numbered register is loaded from the lowest memory address, through to the
highest-numbered register from the highest memory address. See also Encoding of lists of ARM core
registers on page A8-295.
Encoding T1 does not support a list containing only one register. If an LDMDB instruction with just
one register in the list is assembled to Thumb, it is assembled to the equivalent LDR{}{}
, [, #-4]{!} instruction.
The SP can be in the list in ARM instructions, but not in Thumb instructions. However, ARM
instructions that include the SP in the list are deprecated.
The PC can be in the list. If it is, the instruction branches to the address loaded to the PC. In
ARMv5T and above, this is an interworking branch, see Pseudocode details of operations on ARM
core registers on page A2-47. In Thumb instructions, if the PC is in the list:
• the LR must not be in the list
• the instruction must be either outside any IT block, or the last instruction in an IT block.
For the ARM instruction set, ARM deprecates including both LR and PC in the list.
Instructions with the base register in the list and ! specified are only available in the ARM
instruction set before ARMv7, and ARM deprecates the use of such instructions. The value of the
base register after such an instruction is UNKNOWN.
LDMEA is a pseudo-instruction for LDMDB, referring to its use for popping data from Empty Ascending stacks.
The pre-UAL syntaxes LDMDB and LDMEA are equivalent to LDMDB.
Operation
if ConditionPassed() then
EncodingSpecificOperations(); NullCheckIfThumbEE(n);
address = R[n] - 4*BitCount(registers);
for i = 0 to 14
if registers == ‘1’ then
R[i] = MemA[address,4]; address = address + 4;
if registers<15> == ‘1’ then
LoadWritePC(MemA[address,4]);
if wback && registers == ‘0’ then R[n] = R[n] - 4*BitCount(registers);
if wback && registers == ‘1’ then R[n] = bits(32) UNKNOWN;
Exceptions
Data Abort.