rk3399 android9 mipi屏调试

最新推荐文章于 2023-09-08 00:03:00 发布

YY2065

最新推荐文章于 2023-09-08 00:03:00 发布

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分类专栏： # rk3399

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本文详细介绍了 DSI (Display Serial Interface) 显示配置的各项参数设置，包括面板兼容性、电源供应、重置延迟等，并提供了详细的初始化序列及显示定时配置。

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&hdmi_dp_sound {
	status = "okay";
};

&hdmi {
	status = "okay";
};

&hdmi_in_vopb {
	status = "disabled";
};

&dsi_in_vopl {
	status = "disabled";
};

&dsi_in_vopb {
	status = "okay";
};

&dsi {
	status = "okay";
	  panel@0 {
		compatible = "simple-panel-dsi";
		reg = <0>;
		power-supply = <&vcc3v3_s0>;
		backlight = <&backlight>;
		//reset-gpios = <&gpio1 RK_PB1 GPIO_ACTIVE_LOW>;
		//enable-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
				
		dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
			      MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>;
		dsi,format = <MIPI_DSI_FMT_RGB888>;
		dsi,lanes  = <4>;

		reset-delay-ms = <40>;
		enable-delay-ms = <40>;
		prepare-delay-ms = <40>;
		unprepare-delay-ms = <40>;
		disable-delay-ms = <40>;
		
		panel-init-sequence = [ 
			39 00 03 E0 AB BA 
			39 00 03 E1 BA AB 
			39 00 05 B1 10 01 47 FF   
			39 00 07 B2 06 06 04 50 50 14 
			39 00 04 B3 56 53 00 
			39 00 04 B4 33 30 04   
			39 00 08 B6 B0 00 00 10 00 10 00 
			39 00 08 B8 05 12 29 49 48 00 00 
			39 00 27 B9 7C 52 3B 2F 2B 2B 20 0A 26 27 29 4B 3D 4c 3C 39 2C 1A 06 7C 42 2B 1a 16 18 13 01 20 25 29 4f 45 58 4C 39 2C 1A 06
			39 00 11 C0 66 43 12 34 22 22 24 44 90 04 90 04 0F 00 00 C1 
			39 00 0b C1 31 54 02 83 90 04 90 04 54 80 
			39 00 0d C2 13 09 08 89 08 11 22 20 44 BB 18 00 
			39 00 17 C3 80 40 00 06 07 00 01 01 05 02 02 02 02 02 02 00 00 0E 0F 0C 0D 02 
			39 00 17 C4 00 00 00 06 07 00 01 01 05 02 02 02 02 02 02 00 00 0E 0F 0C 0D 02 		
			39 00 04 C5 E8 85 76   
			39 00 03 C6 00 00  
			39 00 07 C8 10 00 31 42 34 16 
			39 00 03 CA CB 43 
			39 00 05 CC 2E 02 04 08 
			39 00 09 CD 0E 20 64 00 0A 6B 06 B3 
			39 00 05 D2 E3 2B 38 00   
			39 00 0c D4 00 01 00 0E 04 44 08 10 00 00 00 
			39 00 09 E6 00 01 FF FF FF FF FF FF 
			39 00 06 F0 12 03 20 00 FF 
			39 00 02 F3 00
			15 96 01 11 
			15 64 01 29 		
		];
		

     display-timings {
			native-mode = <&timing0>;
			timing0: timing0 {
				clock-frequency = <68000000>;
				hactive = <800>;
				vactive = <1280>;

				hfront-porch = <16>;
				hback-porch = <48>;
				hsync-len = <16>;

				vfront-porch = <8>;
				vback-porch = <4>;
				vsync-len = <4>;
				
				hsync-active = <0>;
				vsync-active = <0>;
				de-active = <0>;
				pixelclk-active = <0>;
			};
		};
	};
};


&route_dsi {
	status = "okay";
	connect = <&vopb_out_dsi>;
};

&vopb {
	assigned-clocks = <&cru DCLK_VOP0_DIV>;
	assigned-clock-parents = <&cru PLL_CPLL>;
};

&vopl {
	assigned-clocks = <&cru DCLK_VOP1_DIV>;
	assigned-clock-parents = <&cru PLL_VPLL>;
};