WinstonQQM的博客

Verilog练习：HDLBits笔记19

WinstonQQM — Wed, 01 Dec 2021 16:53:09 +0800

五、Reading Simulations Writing Testbenches 1、Clock Problem Statement： You are provided a module with the following declaration: module dut ( input clk ) ; Write a testbench that creates one instance of moduledut(with any instance name), and create ..

Verilog练习：HDLBits笔记18

WinstonQQM — Wed, 01 Dec 2021 13:00:50 +0800

五、Reading Simulations Build a circuit from a simulation 1、Combinational circuit 1 Problem Statement： This is a combinational circuit. Read the simulation waveforms to determine what the circuit does, then implement it. module top_module ( inp

Verilog练习：HDLBits笔记17

WinstonQQM — Tue, 30 Nov 2021 11:20:23 +0800

五、Reading Simulations Finding bugs in codes 1、MUX Problem Statement： This 8-bit wide 2-to-1 multiplexer doesn't work. Fix the bug(s). //Source Code module top_module ( input sel, input [7:0] a, input [7:0] b, output out ); ass

Verilog练习：HDLBits笔记16

WinstonQQM — Mon, 29 Nov 2021 14:55:45 +0800

四、Sequential Logic Building Larger Circuits 1、Counter with period 1000 Problem Statement： Build a counter that counts from 0 to 999, inclusive, with a period of 1000 cycles. The reset input is synchronous, and should reset the counter to 0. mod..

Verilog练习：HDLBits笔记15

WinstonQQM — Sun, 28 Nov 2021 21:11:47 +0800

四、Sequential Logic Finite State Machines 1、Simple FSM 1(asynchronous reset) Problem Statement： This is a Moore state machine with two states, one input, and one output. Implement this state machine. Notice that the reset state is B. module top_m.

Verilog练习：HDLBits笔记14

WinstonQQM — Sun, 14 Nov 2021 21:33:49 +0800

四、Sequential Logic More Circuits 1、Rule 90 Problem Statement： In this circuit, create a 512-cell system (q[511:0]), and advance by one time step each clock cycle. Theloadinput indicates the state of the system should be loaded withdata[511:0]. Ass...

Verilog练习：HDLBits笔记13

WinstonQQM — Sat, 13 Nov 2021 20:15:51 +0800

四、Sequential Logic Shift Registers 1、4-bit shift register Problem Statement： Build a 4-bit shift register (right shift), with asynchronous reset, synchronous load, and enable. areset: Resets shift register to zero. load: Loads shift register with.

Verilog练习：HDLBits笔记12

WinstonQQM — Sat, 13 Nov 2021 13:23:30 +0800

四、Sequential Logic Counters 1、Four-bit binary counter Problem Statement： Build a 4-bit binary counter that counts from 0 through 15, inclusive, with a period of 16. The reset input is synchronous, and should reset the counter to 0.

Verilog练习：HDLBits笔记11

WinstonQQM — Tue, 09 Nov 2021 12:47:55 +0800

四、Sequential Logic Latches and Flip-Flops 1、D flip-flop Problem Statement： Create a single D flip-flop. module top_module ( input clk, input d, output reg q ); always@(posedge clk)begin q = d; end endmodule 2..

Verilog练习：HDLBits笔记10

WinstonQQM — Mon, 08 Nov 2021 21:35:23 +0800

三、Circuits Combinational logic-Karnaugh Map to Circuit 1、3-variable Problem Statement： mplement the circuit described by the Karnaugh map below. module top_module( input a, input b, input c, output out ); assign out = a | b

Verilog练习：HDLBits笔记9

WinstonQQM — Sun, 07 Nov 2021 17:50:29 +0800

三、Circuits Combinational logic-Arithmetic Circuits 1、Half adder Problem Statement： Create a half adder. A half adder adds two bits (with no carry-in) and produces a sum and carry-out. module top_module( input a, b, output cout, sum );

Verilog练习：HDLBits笔记8

WinstonQQM — Sun, 07 Nov 2021 15:49:16 +0800

三、Circuits Combinational logic-Multiplexers 1、2-to-1 Multiplexer Problem Statement： Create a one-bit wide, 2-to-1 multiplexer. When sel=0, choose a. When sel=1, choose b. module top_module( input a, b, sel, output out ); always@(*)beg

Verilog练习：HDLBits笔记7

WinstonQQM — Sun, 07 Nov 2021 15:16:17 +0800

三、Circuits Combinational logic-Basic Gates 1、Wire Problem Statement： mplement the following circuit: module top_module ( input in, output out ); assign out = in; endmodule 2、GND Problem Statement： Implement the following circ.

Verilog练习：HDLBits笔记6

WinstonQQM — Wed, 03 Nov 2021 18:34:20 +0800

二、Verilog Language More Verilog Features 1、Conditional ternary operator Problem Statement： Given four unsigned numbers, find the minimum. Unsigned numbers can be compared with standard comparison operators (a < b). Use the conditional operator to m

Verilog练习：HDLBits笔记5

WinstonQQM — Tue, 02 Nov 2021 21:11:31 +0800

二、Verilog Language Procedures 1、Always blocks(Combinational) Problem Statement：

Verilog练习：HDLBits笔记4

WinstonQQM — Mon, 01 Nov 2021 20:21:28 +0800

二、Verilog Language Modules：Hierarchy 1、Modules Problem Statement： The figure below shows a very simple circuit with a sub-module.In this exercise, create one instanceof module mod_a then connect the module's three pins (in1，in2，and out) to your top-le

Verilog练习：HDLBits笔记3

WinstonQQM — Sat, 30 Oct 2021 17:26:22 +0800

二、Verilog Language Vectors 1、Vectors Problem Statement： Build a circuit that has one 3-bit input, then outputs the same vector, and also splits it into three separate 1-bit outputs. Connect output o0 to the input vector's position 0，o1 to position 1,.

Verilog练习：HDLBits笔记2

WinstonQQM — Fri, 29 Oct 2021 21:28:00 +0800

二、Verilog Language Basics 1、Simple wire Problem Statement： Create a module with one input and one output that behaves like a wire. module top_module( input in, output out ); assign out = in; endmodule 2、four wires Problem Statement：

Verilog练习：HDLBits笔记1

WinstonQQM — Fri, 29 Oct 2021 12:39:31 +0800

一、Getting Started 1、Getting Started Problem Statement： Build a circuit with no inputs and one output. That output should always drive 1 (or logic high). module top_module( output one ); // Insert your code here assign one = 1'd1; endmodule .