Lab 1 CMOS Inverter

Lab 1 CMOS Inverter (100 pts)
The objective of this lab is to design an inverter with symmetric output rise and fall times (matched within
5%) and minimal Area-Delay Product (ADP). 10 points will be assigned based on the ranking of your
ADP (refer to point 3 in Section D).
Environment temperature of 85 ℃ and Vdd = 1.1V will be used throughout this project.
Section A: Schematic and Symbol (10 pts)
1. [8pt] In this section, please follow the tutorial to draw the schematic of an inverter. The devices we are
using are PMOS_VTG and NMOS_VTG in the library NCSU_Devices_FreePDK45. You have to choose
the size of the transistors. The inverter should fit all the following requirements: ● It has symmetric
output rise and fall times (matched within 5%)
● Pin names: VDD, GND, IN, OUT (all uppercase)
In DC analysis, find and label the point VM where Vin = Vout
. What do you expect the ratio to be between
VM and Vdd when the output rise/fall times are symmetric?
By varying the (W/L)p and (W/L)n ratio, you can change the DC operating point. Please choose the values
carefully. You are going to draw the layout with the same transistor size, and part of the score will be
evaluated by the Area-Delay Product. Explain the reasons behind your decisions. We expect you to
apply some theoretical analysis here (you can refer to related slides to facilitate th