Quartus Prime 275080警告 pin name already exists

最新推荐文章于 2025-04-23 23:15:09 发布

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最新推荐文章于 2025-04-23 23:15:09 发布

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本文介绍了解决QuartusPrime中因总线命名导致的编译错误问题。当原理图中的总线命名如a[11..0]与单独命名如a11共存时，软件会报错。文章提供了修改设置避免冲突的方法，并解释了不同版本QuartusII软件对总线元素的不同命名规则。

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Quartus Prime 275080警告

Quarus Prime中如果有总线命名分别为 a[11..0] 和 a11，则编译的时候会报错，原因是原理图分解的时候简单的把a[11..0]分解成了 a11,a10,a9….a0 这样的话就出现了命名冲突.

解决办法

Assignments -> Settings -> Analysis and Synthesis Settings -> More Settings

Block Design Naming and change value from “Auto” to “Quartus II”

参考

I solved this problem.

This problem associate with naming rules in Quartus II for cases with schematic.

Information from Quartus 13.0 Help:

CAUSE:

You created a Graphic Design File (GDF) or Block Design File (BDF) with the Max+Plus II software or with an older version of the Quartus II software. The Max+Plus II software had limited support for bus names in schematics and would sometimes rename the elements in the bus to work around these limitations. For example, it would rename bus names such as a[1..0], b[1], and b[0] to a1, a0, b1, and b0 respectively. The Quartus II software initially kept this behavior for backwards compatibility, but now supports a mode that preserves the natural bus names (with brackets) in your design. However, to avoid changing the behavior of the software for existing designs, the Quartus II continues to use the older naming conventions for legacy BDF and GDF design files. For new schematics, the Quartus II software preserves the original names in the design during compilation.

In this case, the Quartus II software renamed the elements in the specified bus. Refer to the sub-messages for the names you should use when making assignments. If you make assignments on the original names, they will be ignored. For more information on schematic naming rules, refer to BDF Naming Rules.

ACTION:

If you want to preserve your bus names, set the Block Design Naming logic option to Quartus II. If you have existing assignments to the modified names and do not wish to change your working design, set the Block Design Naming logic option to Max+Plus II to eliminate this warning without changing the behavior.

You can also update your BDF file to use Quartus II naming rules by clicking Save As, then choosing Block Diagram/Schematic File using Quartus II naming rules (*.bdf), and then saving it.
Way to solve this problem:

Go to Assignments -> Settings -> Analysis and Synthesis Settings -> More Settings

Go to Block Design Naming and change value from “Auto” to “Quartus II”
Instance Naming Rules for Pin Names in the Block Editor

Quartus II software version 7.1 and earlier naming scheme:

When a bus is split, it is converted into a group of pins, and each pin has a unique name. The name of each pin is the base name of the bus, with the index of the pin appended after the base name.

If a bus a[0..3] is split, 4 pins are created: a0, a1, a2, and a3

Note: Use a0 to refer to the first bit of the bus.

Quartus II software version 7.2 and later naming scheme:

When a bus is split, it is converted into a group of pins, and each pin has a unique name. The name of each pin is the base name of the bus, followed by a pair of square brackets, with the index of the pin between the brackets.

If a bus a[0..3] is split, 4 pins are created: a[0], a[1], a[2], and a[3]

Note: Use a[0] to refer to the first bit of the bus.