IC数字前端设计开发4(vim语法高亮---verilog/systemverilog)

来自：https://blog.youkuaiyun.com/sxlwzl/article/details/23753081

来自：https://www.vim.org/scripts/script.php?script_id=1586

来自：https://blog.youkuaiyun.com/zhajio/article/details/45014711

 

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description

This script extends Verilog syntax highlighting, which comes along with Vim 6.3, and adds SystemVerilog stuff to it. It will recognize Verilog and SystemVerilog syntax in *.v, *.vh and *.sv files. The new syntax is named as "verilog_systemverilog". If your scripts are loaded correctly, you should see this syntax name when you execute the Vim command ":set syntax?" in your Verilog/SystemVerilog files.