BIOS--INT 0x10

在没有操作系统的情况下,使用 BIOS 加载一个 x86 16 位汇编语言程序,在屏幕上显示一串字符串。该程序用到了 BIOS INT 0x10 中断,该中断的详细用法在以下链接处。

https://blog.youkuaiyun.com/qq_40169767/article/details/101511805

汇编语言代码:

! 
! boot.s -- bootsect.s 的框架程序。用代码 0x70 替换串 msg1 中 1 字符,
! 然后在屏幕第 1 行显示。
!

.globl begtext, begdata, begbss, endtext, enddata, endbss   ! 全局标识符,供 ld86 
                                                            ! 链接使用
.text       ! 正文段
begtext:
.data       ! 数据段
begdata:
.bss        ! 未初始化数据段
begbss:
.text       ! 正文段
BOOTSEG = 0x07c0        ! BIOS 加载 bootsect 代码的原始段地址

entry start
start:
        jmpi    go, BOOTSEG ! 段间跳转。CS=BOOTSEG(0x07c0), IP=go
go:     mov     ax, cs      ! 初始化 DS、ES 寄存器。DS=ES=0x07c0
        mov     ds, ax
        mov     es, ax
        mov     [msg1+17], ah   ! 0x07 的 ascii 码代表响铃一声,在字符串最后加一声响铃
        mov     cx, #20     ! 串长度。供显示 20 个字符,包括回车、换行
        mov     dx, #0x1004 ! DH、DL 为起始行列。字符串将显示在屏幕第 17 行、第 5 列处
        mov     bx, #0x000c ! BL 为属性。字符显示属性(淡红色)
        mov     bp, #msg1   ! ES:BP=串地址。指向要显示的字符串(中断请求要用到)
        mov     ax, #0x1301 ! AH、AL 表示 0x10 中断的功能。写字符串并移动光标到串结尾处
        int     0x10        ! BIOS 调用 0x10 中断,根据 ax 寄存器,ah=13 表示显示字符串
                            ! al=01 表示彩色显示
loop1:  jmp     loop1
msg1:   .ascii  "Loading system..."
        .byte 13, 10
.org 510                    ! 将 IP 指向 510 处,之后 IP 从 510 开始
        .word 0xAA55        ! 双字,到此处为 512 个字节
.text
endtext:
.data
enddata:
.bss
endbss:
                         

屏幕显示的结果:
在这里插入图片描述


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这是设备树的信息,请结合进行分析 / { cpus { #address-cells = <0x01>; #size-cells = <0x00>; cpu@0 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x80000>; enable-method = "spin-table"; cpu-release-addr = <0x00 0xfff8>; }; cpu@1 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x80100>; enable-method = "spin-table"; cpu-release-addr = <0x00 0xfff8>; }; cpu@2 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x80200>; enable-method = "spin-table"; cpu-release-addr = <0x00 0xfff8>; }; cpu@3 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x80300>; enable-method = "spin-table"; cpu-release-addr = <0x00 0xfff8>; }; cpu@4 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x90000>; enable-method = "spin-table"; cpu-release-addr = <0x00 0xfff8>; }; cpu@5 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x90100>; enable-method = "spin-table"; cpu-release-addr = <0x00 0xfff8>; }; cpu@6 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x90200>; enable-method = "spin-table"; cpu-release-addr = <0x00 0xfff8>; }; cpu@7 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x90300>; enable-method = "spin-table"; cpu-release-addr = <0x00 0xfff8>; }; }; cpu_extra_info { compatible = "cpu_info,extra_info"; cpu_desc = "1230"; cpu_num = <0x08>; cpu_version = "HI1230V100"; }; interrupt-controller@c1000000 { compatible = "arm,gic-v3"; #interrupt-cells = <0x03>; #address-cells = <0x02>; #size-cells = <0x02>; ranges; interrupt-controller; #redistributor-regions = <0x01>; redistributor-stride = <0x00 0x40000>; reg = <0x00 0xc1000000 0x00 0x10000 0x00 0xc1100000 0x00 0x200000>; phandle = <0x01>; }; timer { compatible = "arm,armv8-timer"; interrupts = <0x01 0x0d 0x08 0x01 0x0e 0x08 0x01 0x0b 0x08 0x01 0x0a 0x08>; }; pmu { compatible = "arm,armv8-pmuv3"; interrupts = <0x01 0x07 0x08>; }; peripherals { compatible = "simple-bus"; #address-cells = <0x01>; #size-cells = <0x01>; ranges = <0x00 0x00 0x00 0xffffffff>; refclk200mhz { compatible = "fixed-clock"; #clock-cells = <0x00>; clock-frequency = <0xbebc200>; clock-output-names = "refclk200mhz"; phandle = <0x02>; }; uart@fa510000 { compatible = "snps,dw-apb-uart"; #address-cells = <0x01>; #size-cells = <0x00>; reg = <0xfa510000 0x10000>; interrupts = <0x00 0x67 0x04>; clocks = <0x02>; clock-names = "apb_pclk"; reg-shift = <0x02>; }; watchdog: wtd@fa0a290c { compatible = "analog,adm706"; reg = <0xfa0a290c 0x1>; /* 寄存器喂狗*/ status = "okay"; }; sdhci@fb400000 { compatible = "hisilicon,sdhci-hi309a"; reg = <0xfb400000 0x10000>; #address-cells = <0x01>; #size-cells = <0x00>; interrupts = <0x00 0x61 0x04>; bus-width = <0x04>; max-frequency = <0x5f5e100>; mmc-hs200-1_8v; non-removable; wp-inverted; use-pio; sdc_ctrl_reg = <0xfa053238>; hc-type = <0x00>; mmcard@0 { reg = <0x00>; compatible = "mmc-card"; broken-hpi; }; }; uart@fa520000 { compatible = "snps,dw-apb-uart"; #address-cells = <0x01>; #size-cells = <0x00>; reg = <0xfa520000 0x10000>; interrupts = <0x00 0x68 0x04>; current-speed = <0x2580>; clocks = <0x02>; clock-names = "apb_pclk"; reg-shift = <0x02>; }; }; subctrl { compatible = "hisi_subctrl"; #address-cells = <0x02>; #size-cells = <0x02>; peri_subctrl@0 { reg = <0x00 0xfa050000 0x00 0x10000>; reg-name = "subctrl"; subctrl-name = "peri_sub"; #clock-cells = <0x01>; #reset-cells = <0x01>; phandle = <0x05>; }; poe_subctrl@0 { reg = <0x00 0xc0050000 0x00 0x10000>; reg-name = "subctrl"; subctrl-name = "poe_sub"; #clock-cells = <0x01>; #reset-cells = <0x01>; phandle = <0x03>; }; sppe_subctrl@0 { reg = <0x00 0xd8850000 0x00 0x10000>; reg-name = "subctrl"; subctrl-name = "sppe0_sub"; #clock-cells = <0x01>; #reset-cells = <0x01>; phandle = <0x09>; }; eth_subctrl@0 { reg = <0x00 0xf5050000 0x00 0x10000>; reg-name = "subctrl"; subctrl-name = "eth_sub"; #clock-cells = <0x01>; #reset-cells = <0x01>; phandle = <0x04>; }; sysctrl@0 { reg = <0x00 0xfa0a0000 0x00 0x10000>; reg-name = "subctrl"; subctrl-name = "sys_ctrl"; #clock-cells = <0x01>; #reset-cells = <0x01>; }; hilinkmux_subctrl@0 { reg = <0x00 0xf50c0000 0x00 0x10000>; reg-name = "subctrl"; subctrl-name = "hilinkmux_sub"; #clock-cells = <0x01>; #reset-cells = <0x01>; }; }; poe { compatible = "hisi, poe-v100"; #address-cells = <0x02>; #size-cells = <0x02>; interrupts = <0x00 0x1a5 0x01 0x00 0x1a6 0x01 0x00 0x1a7 0x01 0x00 0x1a8 0x01 0x00 0x1a9 0x01 0x00 0x1aa 0x01 0x00 0x1ab 0x01 0x00 0x1ac 0x01 0x00 0x1ad 0x01 0x00 0x1ae 0x01 0x00 0x1af 0x01 0x00 0x1b0 0x01 0x00 0x1b1 0x01 0x00 0x1b2 0x01 0x00 0x1b3 0x01 0x00 0x1b4 0x01>; poe_int_index = <0x00>; status = "okay"; vf_num = <0x01>; pf { reg = <0x00 0xc7000000 0x00 0x800000>; poe_acc_pf = <0x00 0xc7000000 0x00 0x800000>; poe_acc_add_pkt_baddr_pf = <0x00 0xc0480000 0x00 0x10000>; poe_forward_tm_baddr_pf = <0x00 0xf4880100 0x00 0x10000>; poe_send_tm_baddr_pf = <0x00 0xf48800c0 0x00 0x10000>; poe_add_tm_credit_baddr_pf = <0x00 0xf4006000 0x00 0x10000>; poe_send_bmu_baddr_pf = <0x00 0xc03851e0 0x00 0x10000>; poe_send_sppe_credit_baddr_pf = <0x00 0xd000f0d0 0x00 0x10000>; poe_send_sppe_emio_credit_baddr_pf = <0x00 0xd000f0c0 0x00 0x10000>; poe_msg_sppe_baddr_pf = <0x00 0xd0040100 0x00 0x10000>; poe_send_sec_credit_baddr_pf = <0x00 0xfd805604 0x00 0x10000>; poe_msg_sec_baddr_pf = <0x00 0xfd805840 0x00 0x10000>; lcpu_mode = <0x02>; clk_poe_group0 { clk_group_id = <0x00>; clocks = <0x03 0x00>; clock-names = "CLK_POE_CLK0"; at_user = <0x01>; }; rst_poe_group0 { rst_group_id = <0x00>; resets = <0x03 0x00>; reset-names = "RST_POE_RST0"; at_user = <0x01>; }; }; vf0 { reg = <0x00 0xc7800000 0x00 0x100000 0x00 0xcc000000 0x00 0x800000 0x00 0xc0480000 0x00 0x20000>; reg-names = "reg\0poe_grp_vf\0poe_acc_vf"; cpu_get_grp_pbase = <0x00 0xcc000000 0x00 0x800000>; ovfl_addr = <0x04 0xC0100000 0x00 0x400000>; // 4M reserv vqi_def_map_mode = <0x01>; vf_endian = <0x00>; vcpu_num = <0x10>; vcpu_grp_num = <0x10>; vacc_grp_num = <0x12>; interrupt-names = "irq_poe0_group12\0irq_poe0_group13"; }; }; ppe { compatible = "hisi, ppe-v110"; #address-cells = <0x02>; #size-cells = <0x02>; bd_version = <0x00>; status = "okay"; pf { reg = <0x00 0xf0000000 0x00 0x800000>; vf_num = <0x01>; deft_fw_mod = <0x01>; deft_fw_tnl = <0x00>; /* enable rss use for kernel path enable_rss = <0x01>; mam_pool_num_vf0 = <0x04>; mam_pool_depth_vf0 = <0x100 0x100 0x100 0x100>; */ /* enable rss use for dpdk path enable_rss = <0x01>; mam_pool_num_vf0 = <0x08>; mam_pool_depth_vf0 = <512 0x40 0x40 0x40 0x40 0x40 0x40 0x40>; */ enable_rss = <0x00>; // 0 means disable rss mam_pool_num_vf0 = <0x10>; mam_pool_depth_vf0 = <0x40 0x40 0x40 0x40 0x40 0x40 0x40 0x40 0x40 0x40 0x40 0x40 0x40 0x40 0x40 0x40>; ppe_cport_alloc_num = <0x1a>; smmu_type = <0x00>; fw_grp_num_per_vf = <0x10>; bd_endian = <0x00>; fw1_flow_res_range = <0x00 0x00>; fw1_flow_bit_mode = <0x01>; fw2_flow_res_range = <0x01 0x01>; fw2_flow_bit_mode = <0x01>; ig1_flow_res_range = <0x00 0x00>; ig1_flow_bit_mode = <0x02>; ig2_flow_res_range = <0x01 0x01>; ig2_flow_bit_mode = <0x02>; eg1_flow_res_range = <0x02 0x02>; eg1_flow_bit_mode = <0x02>; clk_ppe_group_0 { clk_group_id = <0x00>; clocks = <0x04 0x01>; clock-names = "CLK_PPE_CLK0"; at_user = <0x01>; }; rst_ppe_group_0 { rst_group_id = <0x00>; resets = <0x04 0x01 0x04 0x02>; reset-names = "RST_PPE_RST0\0RST_PPE_RST1"; at_user = <0x01>; }; }; vf0 { reg = <0x00 0xf0800000 0x00 0x100000>; buf_endian_mode = <0x00>; buf_adp_en = <0x00>; buf_big_adp_en = <0x00>; }; }; sub_ctrl_c@60000000 { compatible = "hisilicon,peri-subctrl\0syscon"; reg = <0x00 0xfa050000 0x00 0x10000>; phandle = <0x07>; }; mac_serdes { compatible = "mac_serdes"; reg = <0x00 0xf1000000 0x00 0x800000>; chip_id = <0x00>; pf_id = <0x00>; mag_mac_msi_region = <0x00 0x1a>; interrupts = <0x00 0x142 0x01 0x00 0x143 0x01 0x00 0x144 0x01 0x00 0x145 0x01 0x00 0x146 0x01 0x00 0x147 0x01 0x00 0x148 0x01 0x00 0x149 0x01 0x00 0x14a 0x01 0x00 0x14b 0x01 0x00 0x14c 0x01 0x00 0x14d 0x01 0x00 0x14e 0x01 0x00 0x14f 0x01 0x00 0x150 0x01 0x00 0x151 0x01 0x00 0x152 0x01 0x00 0x153 0x01 0x00 0x154 0x01 0x00 0x155 0x01 0x00 0x156 0x01 0x00 0x157 0x01 0x00 0x158 0x01 0x00 0x159 0x01 0x00 0x15a 0x01 0x00 0x15b 0x01>; interrupt-names = "irq_mag_mac0_port0\0irq_mag_mac0_port1\0irq_mag_mac0_port2\0irq_mag_mac0_port3\0irq_mag_mac0_port4\0irq_mag_mac0_port5\0irq_mag_mac0_port6\0irq_mag_mac0_port7\0irq_mag_mac0_port8\0irq_mag_mac0_port9\0irq_mag_mac0_port10\0irq_mag_mac0_port11\0irq_mag_mac0_port12\0irq_mag_mac0_port13\0irq_mag_mac0_port14\0irq_mag_mac0_port15\0irq_mag_mac0_port16\0irq_mag_mac0_port17\0irq_mag_mac0_port18\0irq_mag_mac0_port19\0irq_mag_mac0_port20\0irq_mag_mac0_port21\0irq_mag_mac0_port22\0irq_mag_mac0_port23\0irq_mag_mac0_port24\0irq_mag_mac0_port25"; status = "okay"; clk_mag_group0 { clk_group_id = <0x00>; clocks = <0x04 0x03 0x04 0x04 0x04 0x05 0x04 0x06 0x04 0x07>; clock-names = "CLK_MAG_CLK0\0CLK_MAG_CLK1\0CLK_MAG_CLK2\0CLK_MAG_CLK3\0CLK_MAG_CLK4"; at_user = <0x01>; }; rst_mag_group { rst_group_id = <0x00>; resets = <0x04 0x08 0x04 0x09 0x04 0x0a 0x04 0x0b>; reset-names = "RST_MAG_RST0\0RST_MAG_RST1\0RST_MAG_RST2\0RST_MAG_RST3"; at_user = <0x01>; }; rst_mag_macv110_x4_t_group { rst_group_id = <0x01>; resets = <0x04 0x0c 0x04 0x0d 0x04 0x0e 0x04 0x0f 0x04 0x10 0x04 0x11>; reset-names = "RST_MAG_MACV110_X4_T_00\0RST_MAG_MACV110_X4_T_01\0RST_MAG_MACV110_X4_T_02\0RST_MAG_MACV110_X4_T_03\0RST_MAG_MACV110_X4_T_04\0RST_MAG_MACV110_X4_T_05"; at_user = <0x01>; }; rst_mag_macv110_x4_cfg_group { rst_group_id = <0x02>; resets = <0x04 0x12 0x04 0x13 0x04 0x14 0x04 0x15 0x04 0x16 0x04 0x17 0x04 0x18 0x04 0x19 0x04 0x1a 0x04 0x1b 0x04 0x1c 0x04 0x1d 0x04 0x1e 0x04 0x1f 0x04 0x20 0x04 0x21 0x04 0x22 0x04 0x23 0x04 0x24 0x04 0x25 0x04 0x26 0x04 0x27 0x04 0x28 0x04 0x29>; reset-names = "RST_MAG_MACV110_X4_CFG_00\0RST_MAG_MACV110_X4_CFG_01\0RST_MAG_MACV110_X4_CFG_02\0RST_MAG_MACV110_X4_CFG_03\0RST_MAG_MACV110_X4_CFG_04\0RST_MAG_MACV110_X4_CFG_05\0RST_MAG_MACV110_X4_CFG_06\0RST_MAG_MACV110_X4_CFG_07\0RST_MAG_MACV110_X4_CFG_08\0RST_MAG_MACV110_X4_CFG_09\0RST_MAG_MACV110_X4_CFG_10\0RST_MAG_MACV110_X4_CFG_11\0RST_MAG_MACV110_X4_CFG_12\0RST_MAG_MACV110_X4_CFG_13\0RST_MAG_MACV110_X4_CFG_14\0RST_MAG_MACV110_X4_CFG_15\0RST_MAG_MACV110_X4_CFG_16\0RST_MAG_MACV110_X4_CFG_17\0RST_MAG_MACV110_X4_CFG_18\0RST_MAG_MACV110_X4_CFG_19\0RST_MAG_MACV110_X4_CFG_20\0RST_MAG_MACV110_X4_CFG_21\0RST_MAG_MACV110_X4_CFG_22\0RST_MAG_MACV110_X4_CFG_23"; at_user = <0x01>; }; rst_mag_macv110_x4_core_group { rst_group_id = <0x03>; resets = <0x04 0x2a 0x04 0x2b 0x04 0x2c 0x04 0x2d 0x04 0x2e 0x04 0x2f 0x04 0x30 0x04 0x31 0x04 0x32 0x04 0x33 0x04 0x34 0x04 0x35 0x04 0x36 0x04 0x37 0x04 0x38 0x04 0x39 0x04 0x3a 0x04 0x3b 0x04 0x3c 0x04 0x3d 0x04 0x3e 0x04 0x3f 0x04 0x40 0x04 0x41>; reset-names = "RST_MAG_MACV110_X4_CORE_00\0RST_MAG_MACV110_X4_CORE_01\0RST_MAG_MACV110_X4_CORE_02\0RST_MAG_MACV110_X4_CORE_03\0RST_MAG_MACV110_X4_CORE_04\0RST_MAG_MACV110_X4_CORE_05\0RST_MAG_MACV110_X4_CORE_06\0RST_MAG_MACV110_X4_CORE_07\0RST_MAG_MACV110_X4_CORE_08\0RST_MAG_MACV110_X4_CORE_09\0RST_MAG_MACV110_X4_CORE_10\0RST_MAG_MACV110_X4_CORE_11\0RST_MAG_MACV110_X4_CORE_12\0RST_MAG_MACV110_X4_CORE_13\0RST_MAG_MACV110_X4_CORE_14\0RST_MAG_MACV110_X4_CORE_15\0RST_MAG_MACV110_X4_CORE_16\0RST_MAG_MACV110_X4_CORE_17\0RST_MAG_MACV110_X4_CORE_18\0RST_MAG_MACV110_X4_CORE_19\0RST_MAG_MACV110_X4_CORE_20\0RST_MAG_MACV110_X4_CORE_21\0RST_MAG_MACV110_X4_CORE_22\0RST_MAG_MACV110_X4_CORE_23"; at_user = <0x01>; }; rst_mag_macv110_x1_t_group { rst_group_id = <0x04>; resets = <0x04 0x42 0x04 0x43>; reset-names = "RST_MAG_MACV110_X1_T_00\0RST_MAG_MACV110_X1_T_01"; at_user = <0x01>; }; rst_mag_macv110_x1_cfg_group { rst_group_id = <0x05>; resets = <0x04 0x44 0x04 0x45>; reset-names = "RST_MAG_MACV110_X1_CFG_00\0RST_MAG_MACV110_X1_CFG_01"; at_user = <0x01>; }; rst_mag_macv110_x1_core_group { rst_group_id = <0x06>; resets = <0x04 0x46 0x04 0x47>; reset-names = "RST_MAG_MACV110_X1_CORE_00\0RST_MAG_MACV110_X1_CORE_01"; at_user = <0x01>; }; port0@0 { port_id = <0x00>; port_info = <0x08 0x02 0x00 0x01>; interval_ms = <0x1f4>; optical_los = <0x00>; alos_bypass_flag = <0x00>; badeye_bypass_flag = <0x00>; adapt_act_power = <0x00>; first_link_redo_en = <0x00>; goodeye_filter_cnt = <0x00>; badeye_filter_cnt = <0x03>; dfe_false_time_ms = <0x00>; adapt_en_det = <0x00>; adapt_api = <0x01 0x01 0x00 0x00 0x00 0x00 0x00 0x00>; force_rf_insert_en = <0x01>; }; }; djtag0@0xFA0A0000 { compatible = "hisi_djtag"; djtag_id = <0x00>; reg = <0x00 0xfa0a0000 0x00 0x10000>; }; nandc@fc000000 { compatible = "hisi, v650-nandc"; reg = <0x00 0xfc000000 0x00 0x10000 0x08 0x00 0x00 0x10000>; reg-names = "nfc_reg_map\0nfc_internal_buffer"; clocks = <0x05 0x06>; clock-names = "CLK_NANDC_CLK0"; resets = <0x05 0x06>; reset-names = "RST_NANDC_RST0"; interrupts = <0x00 0x64 0x04>; host_id = <0x00>; nand-bus-width = <0x08>; nand-ecc-mode = "hw"; nand-ecc-step-size = <0x400>; plane_num = <0x01>; status = "okay"; skip_host_reset; nand-ecc-strength = <0x10>; bitflip_threshold = <0x08>; nfc_bus_type = <0x00>; timeout_prog = <0xffffff>; timeout_erase = <0xffffff>; nfc_dma_mode = <0x00>; nfc_pwidth = <0x466>; nfc_opidle = <0xffffff>; chip_num = <0x04>; randomizer = <0x00>; partitions { compatible = "fixed-partitions"; #address-cells = <0x01>; #size-cells = <0x01>; partition@0 { label = "na0"; reg = <0x00 0x10000000>; }; partition@0x10000000 { label = "na1"; reg = <0x10000000 0x30000000>; }; }; }; spi@FA400000 { compatible = "synopsis_spi"; #address-cells = <0x01>; #size-cells = <0x00>; bus-num = <0x00>; reg = <0x00 0xfa400000 0x00 0x10000>; interrupts = <0x00 0xf4 0x04>; clocks = <0x05 0x10>; clock-names = "CLK_SPI_CLK0"; resets = <0x05 0x10>; reset-names = "RST_SPI_RST0"; status = "okay"; num-cs = <0x04>; pinctrl-names = "default"; pinctrl-0 = <0x08>; cs@0 { compatible = "rohm,dh2228fv"; reg = <0x00>; spi-max-frequency = <0x17d7840>; cs_type = <0x01>; gpio_id = <0x48>; }; cs@1 { compatible = "rohm,dh2228fv"; reg = <0x01>; spi-max-frequency = <0x17d7840>; cs_type = <0x01>; gpio_id = <0x49>; }; cs@2 { compatible = "rohm,dh2228fv"; reg = <0x02>; spi-max-frequency = <0x17d7840>; }; cs@3 { compatible = "rohm,dh2228fv"; reg = <0x03>; spi-max-frequency = <0x17d7840>; }; }; spi@FA410000 { compatible = "synopsis_spi"; #address-cells = <0x01>; #size-cells = <0x00>; bus-num = <0x01>; reg = <0x00 0xfa410000 0x00 0x10000>; interrupts = <0x00 0xf5 0x04>; clocks = <0x05 0x11>; clock-names = "CLK_SPI_CLK0"; resets = <0x05 0x11>; reset-names = "RST_SPI_RST0"; status = "okay"; num-cs = <0x04>; cs@0 { compatible = "rohm,dh2228fv"; reg = <0x00>; spi-max-frequency = <0x17d7840>; cs_type = <0x02>; }; cs@1 { compatible = "rohm,dh2228fv"; reg = <0x01>; spi-max-frequency = <0x17d7840>; }; cs@2 { compatible = "rohm,dh2228fv"; reg = <0x02>; spi-max-frequency = <0x17d7840>; }; cs@3 { compatible = "rohm,dh2228fv"; reg = <0x03>; spi-max-frequency = <0x17d7840>; }; }; spi@FA420000 { compatible = "synopsis_spi"; #address-cells = <0x01>; #size-cells = <0x00>; bus-num = <0x02>; reg = <0x00 0xfa420000 0x00 0x10000>; interrupts = <0x00 0xf6 0x04>; clocks = <0x05 0x12>; clock-names = "CLK_SPI_CLK0"; resets = <0x05 0x12>; reset-names = "RST_SPI_RST0"; status = "okay"; num-cs = <0x04>; cs@0 { compatible = "rohm,dh2228fv"; reg = <0x00>; spi-max-frequency = <0x17d7840>; cs_type = <0x01>; gpio_id = <0x27>; }; cs@1 { compatible = "rohm,dh2228fv"; reg = <0x01>; spi-max-frequency = <0x17d7840>; cs_type = <0x01>; gpio_id = <0x28>; }; cs@2 { compatible = "rohm,dh2228fv"; reg = <0x02>; spi-max-frequency = <0x17d7840>; }; cs@3 { compatible = "rohm,dh2228fv"; reg = <0x03>; spi-max-frequency = <0x17d7840>; }; }; spi@FA430000 { compatible = "synopsis_spi"; #address-cells = <0x01>; #size-cells = <0x00>; bus-num = <0x03>; reg = <0x00 0xfa430000 0x00 0x10000>; interrupts = <0x00 0xf7 0x04>; clocks = <0x05 0x13>; clock-names = "CLK_SPI_CLK0"; resets = <0x05 0x13>; reset-names = "RST_SPI_RST0"; status = "okay"; num-cs = <0x04>; cs@0 { compatible = "rohm,dh2228fv"; reg = <0x00>; spi-max-frequency = <0x17d7840>; cs_type = <0x01>; gpio_id = <0xaa>; }; cs@1 { compatible = "rohm,dh2228fv"; reg = <0x01>; spi-max-frequency = <0x17d7840>; cs_type = <0x01>; gpio_id = <0x98>; }; cs@2 { compatible = "rohm,dh2228fv"; reg = <0x02>; spi-max-frequency = <0x17d7840>; }; cs@3 { compatible = "rohm,dh2228fv"; reg = <0x03>; spi-max-frequency = <0x17d7840>; }; }; espi0@FA470000 { compatible = "espi_v100"; resets = <0x05 0x09>; reset-names = "RST_ESPI_RST0"; clocks = <0x05 0x09>; clock-names = "CLK_ESPI_CLK0"; bus-num = <0x00>; reg_info = <0x00 0xfa470000 0x00 0x10000>; remap_reg_info = <0x02 0x00 0x00 0x40000000>; status = "okay"; cs-nums = <0x04>; remap_mode = <0x01>; cs@0 { remap_cfg = <0x01 0x03 0x00 0x00 0x01>; seq_cfg = <0x07 0x00 0x01 0x01 0x03 0xff>; }; cs@1 { remap_cfg = <0x01 0x03 0x00 0x00 0x01>; seq_cfg = <0x07 0x00 0x01 0x01 0x03 0xff>; }; cs@2 { remap_cfg = <0x01 0x03 0x00 0x00 0x01>; seq_cfg = <0x07 0x00 0x01 0x01 0x03 0xff>; }; cs@3 { remap_cfg = <0x01 0x03 0x00 0x00 0x01>; seq_cfg = <0x07 0x00 0x01 0x01 0x03 0xff>; }; }; espi1@FA480000 { compatible = "espi_v100"; resets = <0x05 0x0a>; reset-names = "RST_ESPI_RST0"; clocks = <0x05 0x0a>; clock-names = "CLK_ESPI_CLK0"; bus-num = <0x01>; reg_info = <0x00 0xfa480000 0x00 0x10000>; remap_reg_info = <0x02 0x40000000 0x00 0x40000000>; status = "okay"; cs-nums = <0x02>; remap_mode = <0x01>; cs@0 { remap_cfg = <0x01 0x03 0x00 0x00 0x01>; seq_cfg = <0x07 0x00 0x01 0x01 0x03 0xff>; }; cs@1 { remap_cfg = <0x01 0x03 0x00 0x00 0x01>; seq_cfg = <0x07 0x00 0x01 0x01 0x03 0xff>; }; }; espi2@FA490000 { compatible = "espi_v100"; resets = <0x05 0x0b>; reset-names = "RST_ESPI_RST0"; clocks = <0x05 0x0b>; clock-names = "CLK_ESPI_CLK0"; bus-num = <0x02>; reg_info = <0x00 0xfa490000 0x00 0x10000>; remap_reg_info = <0x02 0x80000000 0x00 0x40000000>; status = "okay"; cs-nums = <0x02>; remap_mode = <0x01>; cs@0 { remap_cfg = <0x01 0x03 0x00 0x00 0x01>; seq_cfg = <0x07 0x00 0x01 0x01 0x03 0xff>; }; cs@1 { remap_cfg = <0x01 0x03 0x00 0x00 0x01>; seq_cfg = <0x07 0x00 0x01 0x01 0x03 0xff>; }; }; espi3@FA4A0000 { compatible = "espi_v100"; resets = <0x05 0x0c>; reset-names = "RST_ESPI_RST0"; clocks = <0x05 0x0c>; clock-names = "CLK_ESPI_CLK0"; bus-num = <0x03>; reg_info = <0x00 0xfa4a0000 0x00 0x10000>; remap_reg_info = <0x02 0xc0000000 0x00 0x40000000>; status = "okay"; cs-nums = <0x02>; remap_mode = <0x01>; cs@0 { remap_cfg = <0x01 0x03 0x00 0x00 0x01>; seq_cfg = <0x07 0x00 0x01 0x01 0x03 0xff>; }; cs@1 { remap_cfg = <0x01 0x03 0x00 0x00 0x01>; seq_cfg = <0x07 0x00 0x01 0x01 0x03 0xff>; }; }; espi4@FA4B0000 { compatible = "espi_v100"; resets = <0x05 0x0d>; reset-names = "RST_ESPI_RST0"; clocks = <0x05 0x0d>; clock-names = "CLK_ESPI_CLK0"; bus-num = <0x04>; reg_info = <0x00 0xfa4b0000 0x00 0x10000>; remap_reg_info = <0x03 0x00 0x00 0x40000000>; status = "okay"; cs-nums = <0x02>; remap_mode = <0x01>; cs@0 { remap_cfg = <0x01 0x03 0x00 0x00 0x01>; seq_cfg = <0x07 0x00 0x01 0x01 0x03 0xff>; }; cs@1 { remap_cfg = <0x01 0x03 0x00 0x00 0x01>; seq_cfg = <0x07 0x00 0x01 0x01 0x03 0xff>; }; }; espi5@FA4C0000 { compatible = "espi_v100"; resets = <0x05 0x0e>; reset-names = "RST_ESPI_RST0"; clocks = <0x05 0x0e>; clock-names = "CLK_ESPI_CLK0"; bus-num = <0x05>; reg_info = <0x00 0xfa4c0000 0x00 0x10000>; remap_reg_info = <0x03 0x40000000 0x00 0x40000000>; status = "okay"; cs-nums = <0x02>; remap_mode = <0x01>; cs@0 { remap_cfg = <0x01 0x03 0x00 0x00 0x01>; seq_cfg = <0x07 0x00 0x01 0x01 0x03 0xff>; }; cs@1 { remap_cfg = <0x01 0x03 0x00 0x00 0x01>; seq_cfg = <0x07 0x00 0x01 0x01 0x03 0xff>; }; }; espi6@FA4D0000 { compatible = "espi_v100"; resets = <0x05 0x0f>; reset-names = "RST_ESPI_RST0"; clocks = <0x05 0x0f>; clock-names = "CLK_ESPI_CLK0"; bus-num = <0x06>; reg_info = <0x00 0xfa4d0000 0x00 0x10000>; remap_reg_info = <0x03 0x80000000 0x00 0x40000000>; status = "okay"; cs-nums = <0x02>; remap_mode = <0x01>; cs@0 { remap_cfg = <0x01 0x03 0x00 0x00 0x01>; seq_cfg = <0x07 0x00 0x01 0x01 0x03 0xff>; }; cs@1 { remap_cfg = <0x01 0x03 0x00 0x00 0x01>; seq_cfg = <0x07 0x00 0x01 0x01 0x03 0xff>; }; }; localbus { compatible = "lbc"; reg = <0x00 0xfa080000 0x00 0x10000>; reg-names = "reg"; interrupts = <0x00 0x62 0x04>; bus_num = <0x00>; clocks = <0x05 0x18>; clock-names = "clk_lbus"; resets = <0x05 0x18>; reset-names = "RST_LBUS_RST0"; cnt = <0x01>; cfg0 = <0x00 0x00 0xfa080000 0x00 0x10000000>; }; usb_host@0xfc200000 { compatible = "xhci-platform"; reg = <0x00 0xfc200000 0x00 0x200000>; interrupts = <0x00 0x73 0x04>; dma-coherent; status = "okay"; }; usb_drd@0xfc400000 { compatible = "xhci-platform"; reg = <0x00 0xfc400000 0x00 0x200000>; interrupts = <0x00 0x71 0x04>; dma-coherent; status = "okay"; }; usb_hisi_0 { compatible = "hisilicon,udrv_usb"; clocks = <0x05 0x15>; clock-names = "host"; resets = <0x05 0x15 0x05 0x33>; reset-names = "host\0host_ext"; reg_base = <0x00 0xfc200000 0x00 0x40000>; host_no = <0x00>; status = "okay"; phy { phy_base = <0x00 0xfa820000 0x00 0x10000>; cfg_off = <0x100>; cfg_mask = <0xfff>; cfg_value = <0x302>; }; }; usb_hisi_1 { compatible = "hisilicon,udrv_usb"; clocks = <0x05 0x16>; clock-names = "host"; resets = <0x05 0x16 0x05 0x34>; reset-names = "host\0host_ext"; reg_base = <0x00 0xfc400000 0x00 0x40000>; host_no = <0x01>; status = "okay"; phy { phy_base = <0x00 0xfa830000 0x00 0x10000>; cfg_off = <0x100>; cfg_mask = <0xfff>; cfg_value = <0x302>; }; }; pcie@d8900000 { compatible = "hisilicon,udrv-pcie-ecam-dt"; reg = <0x0b 0x00 0x00 0x400000 0x00 0xd8900000 0x00 0x80000 0x00 0x700000 0x00 0x00>; reg-names = "config\0dbi\0msi"; bus-range = <0x00 0x03>; ranges = <0x82000000 0x00 0x00 0x0b 0x800000 0x00 0x1f800000>; #address-cells = <0x03>; #size-cells = <0x02>; device_type = "pci"; dma-coherent; msi-trans-type = <0x01>; interrupts = <0x00 0x1f7 0x04>; #interrupt-cells = <0x01>; interrupt-map-mask = <0xf800 0x00 0x00 0x07>; interrupt-map = <0x00 0x00 0x00 0x01 0x01 0x00 0x1f9 0x04 0x00 0x00 0x00 0x02 0x01 0x00 0x1fa 0x04 0x00 0x00 0x00 0x03 0x01 0x00 0x1fb 0x04 0x00 0x00 0x00 0x04 0x01 0x00 0x1fc 0x04>; linux,pci-domain = <0x00>; core-version = <0x00>; clocks_num = <0x02>; clocks = <0x09 0x00 0x09 0x01>; clock-names = "CLK_PCIE_CLK0\0CLK_PCIE_CLK1"; resets_num = <0x01>; resets = <0x09 0x00>; reset-names = "RST_PCIE_RST0"; status = "okay"; port@0 { lanes-nums = <0x01>; max-lanes = <0x01>; max-speed = <0x03>; port-id = <0x00>; lport-id = <0x00>; core-id = <0x00>; port-type = <0x01>; target-speed = <0x01>; probe = <0x01>; }; }; pcie@d8980000 { compatible = "hisilicon,udrv-pcie-ecam-dt"; reg = <0x0b 0x20000000 0x00 0x400000 0x00 0xd8980000 0x00 0x80000 0x00 0x700000 0x00 0x00>; reg-names = "config\0dbi\0msi"; bus-range = <0x00 0x03>; ranges = <0x82000000 0x00 0x00 0x0b 0x20800000 0x00 0x1f800000>; #address-cells = <0x03>; #size-cells = <0x02>; device_type = "pci"; dma-coherent; msi-trans-type = <0x01>; interrupts = <0x00 0x200 0x04>; #interrupt-cells = <0x01>; interrupt-map-mask = <0xf800 0x00 0x00 0x07>; interrupt-map = <0x00 0x00 0x00 0x01 0x01 0x00 0x202 0x04 0x00 0x00 0x00 0x02 0x01 0x00 0x203 0x04 0x00 0x00 0x00 0x03 0x01 0x00 0x204 0x04 0x00 0x00 0x00 0x04 0x01 0x00 0x205 0x04>; linux,pci-domain = <0x01>; core-version = <0x00>; clocks_num = <0x02>; clocks = <0x09 0x02 0x09 0x03>; clock-names = "CLK_PCIE_CLK0\0CLK_PCIE_CLK1"; resets_num = <0x01>; resets = <0x09 0x01>; reset-names = "RST_PCIE_RST0"; status = "okay"; port@0 { lanes-nums = <0x01>; max-lanes = <0x01>; max-speed = <0x03>; port-id = <0x00>; lport-id = <0x01>; core-id = <0x00>; port-type = <0x01>; target-speed = <0x01>; probe = <0x00>; }; }; pcie@d8a00000 { compatible = "hisilicon,udrv-pcie-ecam-dt"; reg = <0x0b 0x40000000 0x00 0x400000 0x00 0xd8a00000 0x00 0x80000 0x00 0x700000 0x00 0x00>; reg-names = "config\0dbi\0msi"; bus-range = <0x00 0x03>; ranges = <0x82000000 0x00 0x00 0x0b 0x40800000 0x00 0x1f800000>; #address-cells = <0x03>; #size-cells = <0x02>; device_type = "pci"; dma-coherent; msi-trans-type = <0x01>; interrupts = <0x00 0x209 0x04>; #interrupt-cells = <0x01>; interrupt-map-mask = <0xf800 0x00 0x00 0x07>; interrupt-map = <0x00 0x00 0x00 0x01 0x01 0x00 0x20b 0x04 0x00 0x00 0x00 0x02 0x01 0x00 0x20c 0x04 0x00 0x00 0x00 0x03 0x01 0x00 0x20d 0x04 0x00 0x00 0x00 0x04 0x01 0x00 0x20e 0x04>; linux,pci-domain = <0x02>; core-version = <0x00>; clocks_num = <0x02>; clocks = <0x09 0x04 0x09 0x05>; clock-names = "CLK_PCIE_CLK0\0CLK_PCIE_CLK1"; resets_num = <0x01>; resets = <0x09 0x02>; reset-names = "RST_PCIE_RST0"; status = "okay"; port@0 { lanes-nums = <0x01>; max-lanes = <0x01>; max-speed = <0x03>; port-id = <0x00>; lport-id = <0x02>; core-id = <0x00>; port-type = <0x01>; target-speed = <0x01>; probe = <0x00>; }; }; pcie@d8a80000 { compatible = "hisilicon,udrv-pcie-ecam-dt"; reg = <0x0b 0x60000000 0x00 0x400000 0x00 0xd8a80000 0x00 0x80000 0x00 0x700000 0x00 0x00>; reg-names = "config\0dbi\0msi"; bus-range = <0x00 0x03>; ranges = <0x82000000 0x00 0x00 0x0b 0x60800000 0x00 0x1f800000>; #address-cells = <0x03>; #size-cells = <0x02>; device_type = "pci"; dma-coherent; msi-trans-type = <0x01>; interrupts = <0x00 0x212 0x04>; #interrupt-cells = <0x01>; interrupt-map-mask = <0xf800 0x00 0x00 0x07>; interrupt-map = <0x00 0x00 0x00 0x01 0x01 0x00 0x214 0x04 0x00 0x00 0x00 0x02 0x01 0x00 0x215 0x04 0x00 0x00 0x00 0x03 0x01 0x00 0x216 0x04 0x00 0x00 0x00 0x04 0x01 0x00 0x217 0x04>; linux,pci-domain = <0x03>; core-version = <0x00>; clocks_num = <0x02>; clocks = <0x09 0x06 0x09 0x07>; clock-names = "CLK_PCIE_CLK0\0CLK_PCIE_CLK1"; resets_num = <0x01>; resets = <0x09 0x03>; reset-names = "RST_PCIE_RST0"; status = "okay"; port@0 { lanes-nums = <0x01>; max-lanes = <0x01>; max-speed = <0x03>; port-id = <0x00>; lport-id = <0x03>; core-id = <0x00>; port-type = <0x01>; target-speed = <0x01>; probe = <0x00>; }; }; pcie@d8b00000 { compatible = "hisilicon,udrv-pcie-ecam-dt"; reg = <0x0b 0x80000000 0x00 0x400000 0x00 0xd8b00000 0x00 0x80000 0x00 0x700000 0x00 0x00>; reg-names = "config\0dbi\0msi"; bus-range = <0x00 0x03>; ranges = <0x82000000 0x00 0x00 0x0b 0x80800000 0x00 0x1f800000>; #address-cells = <0x03>; #size-cells = <0x02>; device_type = "pci"; dma-coherent; msi-trans-type = <0x01>; interrupts = <0x00 0x21b 0x04>; #interrupt-cells = <0x01>; interrupt-map-mask = <0xf800 0x00 0x00 0x07>; interrupt-map = <0x00 0x00 0x00 0x01 0x01 0x00 0x21d 0x04 0x00 0x00 0x00 0x02 0x01 0x00 0x21e 0x04 0x00 0x00 0x00 0x03 0x01 0x00 0x21f 0x04 0x00 0x00 0x00 0x04 0x01 0x00 0x220 0x04>; linux,pci-domain = <0x04>; core-version = <0x00>; clocks_num = <0x02>; clocks = <0x09 0x08 0x09 0x09>; clock-names = "CLK_PCIE_CLK0\0CLK_PCIE_CLK1"; resets_num = <0x01>; resets = <0x09 0x04>; reset-names = "RST_PCIE_RST0"; status = "okay"; port@0 { lanes-nums = <0x02>; max-speed = <0x03>; port-id = <0x00>; lport-id = <0x04>; core-id = <0x00>; port-type = <0x01>; max-lanes = <0x01>; target-speed = <0x01>; probe = <0x00>; }; }; pcie@d8b80000 { compatible = "hisilicon,udrv-pcie-ecam-dt"; reg = <0x0b 0xa0000000 0x00 0x400000 0x00 0xd8b80000 0x00 0x80000 0x00 0x700000 0x00 0x00>; reg-names = "config\0dbi\0msi"; bus-range = <0x00 0x03>; ranges = <0x82000000 0x00 0x00 0x0b 0xa0800000 0x00 0x1f800000>; #address-cells = <0x03>; #size-cells = <0x02>; device_type = "pci"; dma-coherent; msi-trans-type = <0x01>; interrupts = <0x00 0x224 0x04>; #interrupt-cells = <0x01>; interrupt-map-mask = <0xf800 0x00 0x00 0x07>; interrupt-map = <0x00 0x00 0x00 0x01 0x01 0x00 0x226 0x04 0x00 0x00 0x00 0x02 0x01 0x00 0x227 0x04 0x00 0x00 0x00 0x03 0x01 0x00 0x228 0x04 0x00 0x00 0x00 0x04 0x01 0x00 0x229 0x04>; linux,pci-domain = <0x05>; core-version = <0x00>; clocks_num = <0x02>; clocks = <0x09 0x0a 0x09 0x0b>; clock-names = "CLK_PCIE_CLK0\0CLK_PCIE_CLK1"; resets_num = <0x01>; resets = <0x09 0x05>; reset-names = "RST_PCIE_RST0"; status = "okay"; port@0 { lanes-nums = <0x02>; max-speed = <0x03>; port-id = <0x00>; lport-id = <0x05>; core-id = <0x00>; port-type = <0x01>; max-lanes = <0x02>; target-speed = <0x03>; probe = <0x01>; }; }; pcie@d8c00000 { compatible = "hisilicon,udrv-pcie-ecam-dt"; reg = <0x0b 0xc0000000 0x00 0x400000 0x00 0xd8c00000 0x00 0x80000 0x00 0x700000 0x00 0x00>; reg-names = "config\0dbi\0msi"; bus-range = <0x00 0x03>; ranges = <0x82000000 0x00 0x00 0x0b 0xc0800000 0x00 0x1f800000>; #address-cells = <0x03>; #size-cells = <0x02>; device_type = "pci"; dma-coherent; msi-trans-type = <0x01>; interrupts = <0x00 0x256 0x04>; #interrupt-cells = <0x01>; interrupt-map-mask = <0xf800 0x00 0x00 0x07>; interrupt-map = <0x00 0x00 0x00 0x01 0x01 0x00 0x258 0x04 0x00 0x00 0x00 0x02 0x01 0x00 0x259 0x04 0x00 0x00 0x00 0x03 0x01 0x00 0x25a 0x04 0x00 0x00 0x00 0x04 0x01 0x00 0x25b 0x04>; linux,pci-domain = <0x06>; core-version = <0x00>; clocks_num = <0x02>; clocks = <0x09 0x0c 0x09 0x0d>; clock-names = "CLK_PCIE_CLK0\0CLK_PCIE_CLK1"; resets_num = <0x01>; resets = <0x09 0x06>; reset-names = "RST_PCIE_RST0"; status = "okay"; port@0 { lanes-nums = <0x01>; max-lanes = <0x01>; max-speed = <0x03>; port-id = <0x00>; lport-id = <0x06>; core-id = <0x00>; port-type = <0x01>; target-speed = <0x01>; probe = <0x00>; }; }; pcie@d8c80000 { compatible = "hisilicon,udrv-pcie-ecam-dt"; reg = <0x0b 0xe0000000 0x00 0x400000 0x00 0xd8c80000 0x00 0x80000 0x00 0x700000 0x00 0x00>; reg-names = "config\0dbi\0msi"; bus-range = <0x00 0x03>; ranges = <0x82000000 0x00 0x00 0x0b 0xe0800000 0x00 0x1f800000>; #address-cells = <0x03>; #size-cells = <0x02>; device_type = "pci"; dma-coherent; msi-trans-type = <0x01>; interrupts = <0x00 0x25f 0x04>; #interrupt-cells = <0x01>; interrupt-map-mask = <0xf800 0x00 0x00 0x07>; interrupt-map = <0x00 0x00 0x00 0x01 0x01 0x00 0x261 0x04 0x00 0x00 0x00 0x02 0x01 0x00 0x262 0x04 0x00 0x00 0x00 0x03 0x01 0x00 0x263 0x04 0x00 0x00 0x00 0x04 0x01 0x00 0x264 0x04>; linux,pci-domain = <0x07>; core-version = <0x00>; clocks_num = <0x02>; clocks = <0x09 0x0e 0x09 0x0f>; clock-names = "CLK_PCIE_CLK0\0CLK_PCIE_CLK1"; resets_num = <0x01>; resets = <0x09 0x07>; reset-names = "RST_PCIE_RST0"; status = "okay"; port@0 { lanes-nums = <0x01>; max-lanes = <0x01>; max-speed = <0x03>; port-id = <0x00>; lport-id = <0x07>; core-id = <0x00>; port-type = <0x01>; target-speed = <0x01>; probe = <0x00>; }; }; gpio@fa540000 { compatible = "hisilicon,udrv_gpio"; reg = <0x00 0xfa540000 0x00 0x10000>; base = <0x00>; ngpios = <0x20>; host_id = <0x00>; interrupts = <0x00 0x75 0x04>; clocks = <0x05 0x23>; clock-names = "CLK_GPIO_CLK0"; resets = <0x05 0x23>; reset-names = "RST_GPIO_RST0"; gpio-controller; #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; status = "okay"; skip_host_reset; }; gpio@fa550000 { compatible = "hisilicon,udrv_gpio"; reg = <0x00 0xfa550000 0x00 0x10000>; base = <0x20>; ngpios = <0x20>; host_id = <0x01>; interrupts = <0x00 0x76 0x04>; clocks = <0x05 0x24>; clock-names = "CLK_GPIO_CLK0"; resets = <0x05 0x24>; reset-names = "RST_GPIO_RST0"; gpio-controller; #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; status = "okay"; skip_host_reset; }; gpio@fa560000 { compatible = "hisilicon,udrv_gpio"; reg = <0x00 0xfa560000 0x00 0x10000>; base = <0x40>; ngpios = <0x20>; host_id = <0x02>; interrupts = <0x00 0x77 0x04>; clocks = <0x05 0x25>; clock-names = "CLK_GPIO_CLK0"; resets = <0x05 0x25>; reset-names = "RST_GPIO_RST0"; gpio-controller; #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; status = "okay"; skip_host_reset; }; gpio@fa570000 { compatible = "hisilicon,udrv_gpio"; reg = <0x00 0xfa570000 0x00 0x10000>; base = <0x60>; ngpios = <0x20>; host_id = <0x03>; interrupts = <0x00 0x78 0x04>; clocks = <0x05 0x26>; clock-names = "CLK_GPIO_CLK0"; resets = <0x05 0x26>; reset-names = "RST_GPIO_RST0"; gpio-controller; #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; status = "okay"; skip_host_reset; phandle = <0x0c>; }; gpio@fa580000 { compatible = "hisilicon,udrv_gpio"; reg = <0x00 0xfa580000 0x00 0x10000>; base = <0x80>; ngpios = <0x20>; host_id = <0x04>; interrupts = <0x00 0x79 0x04>; clocks = <0x05 0x27>; clock-names = "CLK_GPIO_CLK0"; resets = <0x05 0x27>; reset-names = "RST_GPIO_RST0"; gpio-controller; #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; status = "okay"; skip_host_reset; }; gpio@fa590000 { compatible = "hisilicon,udrv_gpio"; reg = <0x00 0xfa590000 0x00 0x10000>; base = <0xa0>; ngpios = <0x20>; host_id = <0x05>; interrupts = <0x00 0x7a 0x04>; clocks = <0x05 0x28>; clock-names = "CLK_GPIO_CLK0"; resets = <0x05 0x28>; reset-names = "RST_GPIO_RST0"; gpio-controller; #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; status = "okay"; skip_host_reset; }; gpio@fa5A0000 { compatible = "hisilicon,udrv_gpio"; reg = <0x00 0xfa5a0000 0x00 0x10000>; base = <0xc0>; ngpios = <0x20>; host_id = <0x06>; interrupts = <0x00 0x7b 0x04>; clocks = <0x05 0x29>; clock-names = "CLK_GPIO_CLK0"; resets = <0x05 0x29>; reset-names = "RST_GPIO_RST0"; gpio-controller; #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; status = "okay"; skip_host_reset; }; gpio@fa5B0000 { compatible = "hisilicon,udrv_gpio"; reg = <0x00 0xfa5b0000 0x00 0x10000>; base = <0xe0>; ngpios = <0x20>; host_id = <0x07>; interrupts = <0x00 0x7c 0x04>; clocks = <0x05 0x2a>; clock-names = "CLK_GPIO_CLK0"; resets = <0x05 0x2a>; reset-names = "RST_GPIO_RST0"; gpio-controller; #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; status = "okay"; skip_host_reset; phandle = <0x1d>; }; gpio@faa90000 { compatible = "hisilicon,udrv_gpio"; reg = <0x00 0xfaa90000 0x00 0x10000>; base = <0x100>; ngpios = <0x20>; host_id = <0x08>; interrupts = <0x00 0xa5 0x04>; clocks = <0x05 0x2b>; clock-names = "CLK_GPIO_CLK0"; resets = <0x05 0x2b>; reset-names = "RST_GPIO_RST0"; gpio-controller; #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; status = "okay"; skip_host_reset; }; gpio@faaa0000 { compatible = "hisilicon,udrv_gpio"; reg = <0x00 0xfaaa0000 0x00 0x10000>; base = <0x120>; ngpios = <0x20>; host_id = <0x09>; interrupts = <0x00 0xa6 0x04>; clocks = <0x05 0x2c>; clock-names = "CLK_GPIO_CLK0"; resets = <0x05 0x2c>; reset-names = "RST_GPIO_RST0"; gpio-controller; #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; status = "okay"; skip_host_reset; }; i2c@fa380000 { compatible = "hisilicon,udrv_i2c_synopsys"; reg = <0x00 0xfa380000 0x00 0x10000>; interrupts = <0x00 0x106 0x04>; clocks = <0x05 0x19>; clock-names = "CLK_I2C_CLK0"; resets = <0x05 0x19>; reset-names = "RST_I2C_RST0"; clk_rate = <0xbebc200>; bus_id = <0x00>; pinctrl-names = "default\0gpio"; pinctrl-0 = <0x0a>; pinctrl-1 = <0x0b>; sda-gpios = <0x0c 0x09 0x00>; scl-gpios = <0x0c 0x0a 0x00>; status = "okay"; clock-frequency = <0x186a0>; i2c-scl-rising-time-ns = <0x12c>; i2c-scl-falling-time-ns = <0x12c>; i2c-sda-hold-time-ns = <0x190>; i2c-digital-filter-width-ns = <0x19>; }; i2c@fa390000 { compatible = "hisilicon,udrv_i2c_synopsys"; reg = <0x00 0xfa390000 0x00 0x10000>; interrupts = <0x00 0x107 0x04>; clocks = <0x05 0x1a>; clock-names = "CLK_I2C_CLK0"; resets = <0x05 0x1a>; reset-names = "RST_I2C_RST0"; clk_rate = <0xbebc200>; bus_id = <0x01>; pinctrl-names = "default\0gpio"; pinctrl-0 = <0x0d>; pinctrl-1 = <0x0e>; sda-gpios = <0x0c 0x0b 0x00>; scl-gpios = <0x0c 0x0c 0x00>; status = "okay"; clock-frequency = <0x186a0>; i2c-scl-rising-time-ns = <0x12c>; i2c-scl-falling-time-ns = <0x12c>; i2c-sda-hold-time-ns = <0x190>; i2c-digital-filter-width-ns = <0x19>; }; i2c@fa3b0000 { compatible = "hisilicon,udrv_i2c_synopsys"; reg = <0x00 0xfa3b0000 0x00 0x10000>; interrupts = <0x00 0x109 0x04>; clocks = <0x05 0x1c>; clock-names = "CLK_I2C_CLK0"; resets = <0x05 0x1c>; reset-names = "RST_I2C_RST0"; clk_rate = <0xbebc200>; bus_id = <0x03>; pinctrl-names = "default\0gpio"; pinctrl-0 = <0x11>; pinctrl-1 = <0x12>; sda-gpios = <0x0c 0x1b 0x00>; scl-gpios = <0x0c 0x1a 0x00>; status = "okay"; clock-frequency = <0x186a0>; i2c-scl-rising-time-ns = <0x12c>; i2c-scl-falling-time-ns = <0x12c>; i2c-sda-hold-time-ns = <0x190>; i2c-digital-filter-width-ns = <0x19>; }; i2c@fa3c0000 { compatible = "hisilicon,udrv_i2c_synopsys"; reg = <0x00 0xfa3c0000 0x00 0x10000>; interrupts = <0x00 0x10a 0x04>; clocks = <0x05 0x1d>; clock-names = "CLK_I2C_CLK0"; resets = <0x05 0x1d>; reset-names = "RST_I2C_RST0"; clk_rate = <0xbebc200>; bus_id = <0x04>; pinctrl-names = "default\0gpio"; pinctrl-0 = <0x13>; pinctrl-1 = <0x14>; sda-gpios = <0x0c 0x0d 0x00>; scl-gpios = <0x0c 0x0e 0x00>; status = "okay"; clock-frequency = <0x186a0>; i2c-scl-rising-time-ns = <0x12c>; i2c-scl-falling-time-ns = <0x12c>; i2c-sda-hold-time-ns = <0x190>; i2c-digital-filter-width-ns = <0x19>; }; i2c@fa3d0000 { compatible = "hisilicon,udrv_i2c_synopsys"; reg = <0x00 0xfa3d0000 0x00 0x10000>; interrupts = <0x00 0x10b 0x04>; clocks = <0x05 0x1e>; clock-names = "CLK_I2C_CLK0"; resets = <0x05 0x1e>; reset-names = "RST_I2C_RST0"; clk_rate = <0xbebc200>; bus_id = <0x05>; pinctrl-names = "default\0gpio"; pinctrl-0 = <0x15>; pinctrl-1 = <0x16>; sda-gpios = <0x0c 0x0f 0x00>; scl-gpios = <0x0c 0x10 0x00>; status = "okay"; clock-frequency = <0x186a0>; i2c-scl-rising-time-ns = <0x12c>; i2c-scl-falling-time-ns = <0x12c>; i2c-sda-hold-time-ns = <0x190>; i2c-digital-filter-width-ns = <0x19>; }; i2c@fa3e0000 { compatible = "hisilicon,udrv_i2c_synopsys"; reg = <0x00 0xfa3e0000 0x00 0x10000>; interrupts = <0x00 0x10c 0x04>; clocks = <0x05 0x1f>; clock-names = "CLK_I2C_CLK0"; resets = <0x05 0x1f>; reset-names = "RST_I2C_RST0"; clk_rate = <0xbebc200>; bus_id = <0x06>; pinctrl-names = "default\0gpio"; pinctrl-0 = <0x17>; pinctrl-1 = <0x18>; sda-gpios = <0x0c 0x11 0x00>; scl-gpios = <0x0c 0x12 0x00>; status = "okay"; clock-frequency = <0x186a0>; i2c-scl-rising-time-ns = <0x12c>; i2c-scl-falling-time-ns = <0x12c>; i2c-sda-hold-time-ns = <0x190>; i2c-digital-filter-width-ns = <0x19>; }; i2c@fa3f0000 { compatible = "hisilicon,udrv_i2c_synopsys"; reg = <0x00 0xfa3f0000 0x00 0x10000>; interrupts = <0x00 0x10d 0x04>; clocks = <0x05 0x20>; clock-names = "CLK_I2C_CLK0"; resets = <0x05 0x20>; reset-names = "RST_I2C_RST0"; clk_rate = <0xbebc200>; bus_id = <0x07>; pinctrl-names = "default\0gpio"; pinctrl-0 = <0x19>; pinctrl-1 = <0x1a>; sda-gpios = <0x0c 0x13 0x00>; scl-gpios = <0x0c 0x14 0x00>; status = "okay"; clock-frequency = <0x186a0>; i2c-scl-rising-time-ns = <0x12c>; i2c-scl-falling-time-ns = <0x12c>; i2c-sda-hold-time-ns = <0x190>; i2c-digital-filter-width-ns = <0x19>; }; i2c@faab0000 { compatible = "hisilicon,udrv_i2c_synopsys"; reg = <0x00 0xfaab0000 0x00 0x10000>; interrupts = <0x00 0x28e 0x04>; clocks = <0x05 0x21>; clock-names = "CLK_I2C_CLK0"; resets = <0x05 0x21>; reset-names = "RST_I2C_RST0"; clk_rate = <0xbebc200>; bus_id = <0x08>; pinctrl-names = "default\0gpio"; pinctrl-0 = <0x1b>; pinctrl-1 = <0x1c>; sda-gpios = <0x1d 0x10 0x00>; scl-gpios = <0x1d 0x0f 0x00>; status = "okay"; clock-frequency = <0x186a0>; i2c-scl-rising-time-ns = <0x12c>; i2c-scl-falling-time-ns = <0x12c>; i2c-sda-hold-time-ns = <0x190>; i2c-digital-filter-width-ns = <0x19>; }; i2c@faac0000 { compatible = "hisilicon,udrv_i2c_synopsys"; reg = <0x00 0xfaac0000 0x00 0x10000>; interrupts = <0x00 0x28f 0x04>; clocks = <0x05 0x22>; clock-names = "CLK_I2C_CLK0"; resets = <0x05 0x22>; reset-names = "RST_I2C_RST0"; clk_rate = <0xbebc200>; bus_id = <0x09>; pinctrl-names = "default\0gpio"; pinctrl-0 = <0x1e>; pinctrl-1 = <0x1f>; sda-gpios = <0x1d 0x12 0x00>; scl-gpios = <0x1d 0x11 0x00>; status = "okay"; clock-frequency = <0x186a0>; i2c-scl-rising-time-ns = <0x12c>; i2c-scl-falling-time-ns = <0x12c>; i2c-sda-hold-time-ns = <0x190>; i2c-digital-filter-width-ns = <0x19>; }; sfc0@0xfa5C0000 { compatible = "hisi, v120-sfc"; reg = <0x00 0xfa5c0000 0x00 0x10000>; reg-names = "reg"; interrupts = <0x00 0x8b 0x04>; host_id = <0x00>; clocks = <0x05 0x2d>; clock-names = "CLK_SFC_CLK0"; resets = <0x05 0x2d>; reset-names = "RST_SFC_RST0"; status = "okay"; skip_host_reset; flash@0 { compatible = "jedec,spi-nor"; sfc-rx-bus-width = <0x01>; sfc-tx-bus-width = <0x01>; cs = <0x00>; partitions { compatible = "fixed-partitions"; #address-cells = <0x01>; #size-cells = <0x01>; partition@0 { label = "bios0"; reg = <0x00 0x800000>; }; partition@800000 { label = "bootrom_env"; reg = <0x800000 0x800000>; }; partition@900000 { label = "test0"; reg = <0x1000000 0x100000>; }; }; }; flash@1 { compatible = "jedec,spi-nor"; sfc-rx-bus-width = <0x01>; sfc-tx-bus-width = <0x01>; cs = <0x01>; partitions { compatible = "fixed-partitions"; #address-cells = <0x01>; #size-cells = <0x01>; partition@0 { label = "bios1"; reg = <0x00 0x800000>; }; partition@800000 { label = "bootrom_env1"; reg = <0x800000 0x800000>; }; partition@900000 { label = "test1"; reg = <0x1000000 0x100000>; }; }; }; }; sfc1@0xfa4e0000 { compatible = "hisi, v120-sfc"; reg = <0x00 0xfa4e0000 0x00 0x10000>; reg-names = "reg"; interrupts = <0x00 0x8c 0x04>; host_id = <0x01>; clocks = <0x05 0x2e>; clock-names = "CLK_SFC_CLK0"; resets = <0x05 0x2e>; reset-names = "RST_SFC_RST0"; status = "disable"; pinctrl-names = "default"; pinctrl-0 = <0x20>; flash@0 { compatible = "jedec,spi-nor"; sfc-rx-bus-width = <0x01>; sfc-tx-bus-width = <0x01>; cs = <0x00>; partitions { compatible = "fixed-partitions"; #address-cells = <0x01>; #size-cells = <0x01>; partition@0 { label = "bios0"; reg = <0x00 0x800000>; }; partition@800000 { label = "bootrom_env"; reg = <0x800000 0x800000>; }; partition@900000 { label = "test0"; reg = <0x1000000 0x100000>; }; }; }; flash@1 { compatible = "jedec,spi-nor"; sfc-rx-bus-width = <0x01>; sfc-tx-bus-width = <0x01>; cs = <0x01>; partitions { compatible = "fixed-partitions"; #address-cells = <0x01>; #size-cells = <0x01>; partition@0 { label = "bios1"; reg = <0x00 0x800000>; }; partition@800000 { label = "bootrom_env1"; reg = <0x800000 0x800000>; }; partition@900000 { label = "test1"; reg = <0x1000000 0x100000>; }; }; }; }; pmbus0@fa870000 { compatible = "hisilicon,udrv_pmbus"; reg = <0x00 0xfa870000 0x00 0x10000>; pmbus_id = <0x00>; clk_freq_mhz = <0xc8>; avs_wr_unlock_key = <0x5a5a5a5a>; pmbus_wr_unlock_key = <0x5a5a5a5a>; i2c_unlock_key = <0x5a5a5a5a>; status = "okay"; bus_freq_hz = <0x186a0>; scl_high_ratio = <0x32>; scl_low_timeout_ms = <0x1e>; scl_high_idle_us = <0x64>; sda_hold_time_ns = <0x271>; pec_en = <0x00>; }; pmbus1@fa880000 { compatible = "hisilicon,udrv_pmbus"; reg = <0x00 0xfa880000 0x00 0x10000>; pmbus_id = <0x01>; clk_freq_mhz = <0xc8>; avs_wr_unlock_key = <0x5a5a5a5a>; pmbus_wr_unlock_key = <0x5a5a5a5a>; i2c_unlock_key = <0x5a5a5a5a>; status = "okay"; bus_freq_hz = <0x186a0>; scl_high_ratio = <0x32>; scl_low_timeout_ms = <0x1e>; scl_high_idle_us = <0x64>; sda_hold_time_ns = <0x271>; }; pmbus2@fa890000 { compatible = "hisilicon,udrv_pmbus"; reg = <0x00 0xfa890000 0x00 0x10000>; pmbus_id = <0x02>; clk_freq_mhz = <0xc8>; avs_wr_unlock_key = <0x5a5a5a5a>; pmbus_wr_unlock_key = <0x5a5a5a5a>; i2c_unlock_key = <0x5a5a5a5a>; status = "okay"; bus_freq_hz = <0x186a0>; scl_high_ratio = <0x32>; scl_low_timeout_ms = <0x1e>; scl_high_idle_us = <0x64>; sda_hold_time_ns = <0x271>; }; pmbus3@fa8a0000 { compatible = "hisilicon,udrv_pmbus"; reg = <0x00 0xfa8a0000 0x00 0x10000>; pmbus_id = <0x03>; clk_freq_mhz = <0xc8>; avs_wr_unlock_key = <0x5a5a5a5a>; pmbus_wr_unlock_key = <0x5a5a5a5a>; i2c_unlock_key = <0x5a5a5a5a>; status = "okay"; bus_freq_hz = <0x186a0>; scl_high_ratio = <0x32>; scl_low_timeout_ms = <0x1e>; scl_high_idle_us = <0x64>; sda_hold_time_ns = <0x271>; }; sata@0xd8500000 { compatible = "generic-ahci"; reg = <0x00 0xd8500000 0x00 0x100000>; interrupts = <0x00 0x1f3 0x04>; dma-coherent; status = "okay"; }; sata_dfx@0xd8500000 { compatible = "hisilicon,udrv_sata"; reg = <0x00 0xd8500000 0x00 0x100000>; host_id = <0x00>; tx-bitorder = <0x00>; rx-bitorder = <0x01>; clocks = <0x09 0x11>; clock-names = "CLK_SATA_CLK0"; resets = <0x09 0x09>; reset-names = "RST_SATA_RST0"; status = "okay"; }; pinctrl@FA860000 { compatible = "hisi,hi309a-pinctrl"; reg = <0x00 0xfa860000 0x00 0x10000>; status = "okay"; hisi309a-i2c-basic { i2c0_default { hisi,pins = <0xd8 0x30000 0x8dc 0x300fb 0x00 0xffffffff 0xdc 0x30000 0x8e0 0x300fb 0x00 0xffffffff>; phandle = <0x0a>; }; i2c0_gpio { hisi,pins = <0xd8 0x30000 0x8dc 0x300fb 0x06 0xffffffff 0xdc 0x30000 0x8e0 0x300fb 0x06 0xffffffff>; phandle = <0x0b>; }; i2c1_default { hisi,pins = <0x298 0x30000 0xab8 0x300fb 0x00 0xffffffff 0x29c 0x30000 0xabc 0x300fb 0x00 0xffffffff>; phandle = <0x0d>; }; i2c1_gpio { hisi,pins = <0x298 0x30000 0xab8 0x300fb 0x06 0xffffffff 0x29c 0x30000 0xabc 0x300fb 0x06 0xffffffff>; phandle = <0x0e>; }; i2c2_default { hisi,pins = <0x1d8 0x30000 0x9f8 0x300fb 0x01 0xffffffff 0x1d4 0x30000 0x9f4 0x300fb 0x01 0xffffffff>; phandle = <0x0f>; }; i2c2_gpio { hisi,pins = <0x1d8 0x30000 0x9f8 0x300fb 0x06 0xffffffff 0x1d4 0x30000 0x9f4 0x300fb 0x06 0xffffffff>; phandle = <0x10>; }; i2c3_default { hisi,pins = <0x3f0 0x30000 0xc24 0x300fb 0x01 0xffffffff 0x3ec 0x30000 0xc20 0x300fb 0x01 0xffffffff>; phandle = <0x11>; }; i2c3_gpio { hisi,pins = <0x3f0 0x30000 0xc24 0x300fb 0x06 0xffffffff 0x3ec 0x30000 0xc20 0x300fb 0x06 0xffffffff>; phandle = <0x12>; }; i2c4_default { hisi,pins = <0x200 0x30000 0xa20 0x300fb 0x02 0xffffffff 0x204 0x30000 0xa24 0x300fb 0x02 0xffffffff>; phandle = <0x13>; }; i2c4_gpio { hisi,pins = <0x200 0x30000 0xa20 0x300fb 0x06 0xffffffff 0x204 0x30000 0xa24 0x300fb 0x06 0xffffffff>; phandle = <0x14>; }; i2c5_default { hisi,pins = <0x220 0x30000 0xa40 0x300fb 0x01 0xffffffff 0x224 0x30000 0xa44 0x300fb 0x00 0xffffffff>; phandle = <0x15>; }; i2c5_gpio { hisi,pins = <0x220 0x30000 0xa40 0x300fb 0x06 0xffffffff 0x224 0x30000 0xa44 0x300fb 0x06 0xffffffff>; phandle = <0x16>; }; i2c6_default { hisi,pins = <0x12c 0x30000 0x934 0x300fb 0x01 0xffffffff 0x130 0x30000 0x938 0x300fb 0x01 0xffffffff>; phandle = <0x17>; }; i2c6_gpio { hisi,pins = <0x12c 0x30000 0x934 0x300fb 0x06 0xffffffff 0x130 0x30000 0x938 0x300fb 0x06 0xffffffff>; phandle = <0x18>; }; i2c7_default { hisi,pins = <0x2ac 0x30000 0xacc 0x300fb 0x01 0xffffffff 0x2b0 0x30000 0xad0 0x300fb 0x01 0xffffffff>; phandle = <0x19>; }; i2c7_gpio { hisi,pins = <0x2ac 0x30000 0xacc 0x300fb 0x06 0xffffffff 0x2b0 0x30000 0xad0 0x300fb 0x06 0xffffffff>; phandle = <0x1a>; }; i2c8_default { hisi,pins = <0x3f8 0x30000 0xc2c 0x300fb 0x01 0xffffffff 0x3f4 0x30000 0xc28 0x300fb 0x01 0xffffffff>; phandle = <0x1b>; }; i2c8_gpio { hisi,pins = <0x3f8 0x30000 0xc2c 0x300fb 0x06 0xffffffff 0x3f4 0x30000 0xc28 0x300fb 0x06 0xffffffff>; phandle = <0x1c>; }; i2c9_default { hisi,pins = <0x400 0x30000 0xc34 0x300fb 0x01 0xffffffff 0x3fc 0x30000 0xc30 0x300fb 0x01 0xffffffff>; phandle = <0x1e>; }; i2c9_gpio { hisi,pins = <0x400 0x30000 0xc34 0x300fb 0x06 0xffffffff 0x3fc 0x30000 0xc30 0x300fb 0x06 0xffffffff>; phandle = <0x1f>; }; }; hisi309a-sfc-basic { sfc1_default { hisi,pins = <0x0c 0x30000 0x810 0x300fb 0x01 0xffffffff 0x14 0x30000 0x818 0x300fb 0x01 0xffffffff 0x1c 0x30000 0x820 0x300fb 0x01 0xffffffff 0x30 0x30000 0x834 0x300fb 0x01 0xffffffff 0x3c 0x30000 0x840 0x300fb 0x01 0xffffffff 0x40 0x30000 0x844 0x300fb 0x01 0xffffffff 0x44 0x30000 0x848 0x300fb 0x01 0xffffffff 0x48 0x30000 0x84c 0x300fb 0x01 0xffffffff 0x4c 0x30000 0x850 0x300fb 0x01 0xffffffff>; phandle = <0x20>; }; }; hisi309a-spi-basic { spi0_default { hisi,pins = <0x3e0 0x30000 0xc14 0x300fb 0x06 0xffffffff 0x3e4 0x30000 0xc18 0x300fb 0x06 0xffffffff 0x3d4 0x30000 0xc08 0x300fb 0x00 0xffffffff 0x3d8 0x30000 0xc0c 0x300fb 0x00 0xffffffff 0x3dc 0x30000 0xc10 0x300fb 0x00 0xffffffff>; phandle = <0x08>; }; spi1_default { hisi,pins = <0xf4 0x30000 0x8f8 0x300fb 0x06 0xffffffff 0xe8 0x30000 0x8ec 0x300fb 0x01 0xffffffff 0xec 0x30000 0x8f0 0x300fb 0x01 0xffffffff 0xf0 0x30000 0x8f4 0x300fb 0x01 0xffffffff>; }; spi2_default { hisi,pins = <0x148 0x30000 0x954 0x300fb 0x00 0xffffffff 0x14c 0x30000 0x958 0x300fb 0x00 0xffffffff 0x144 0x30000 0x950 0x300fb 0x03 0xffffffff 0x170 0x30000 0x97c 0x300fb 0x03 0xffffffff 0x150 0x30000 0x95c 0x300fb 0x03 0xffffffff>; }; spi3_default { hisi,pins = <0x38c 0x30000 0xbb8 0x300fb 0x00 0xffffffff 0x390 0x20000 0xbbc 0x300fb 0x00 0xffffffff 0x380 0x30000 0xbac 0x300fb 0x03 0xffffffff 0x384 0x30000 0xbb0 0x300fb 0x03 0xffffffff 0x388 0x30000 0xbb4 0x300fb 0x02 0xffffffff>; }; }; }; tsensor@FA0D0000 { compatible = "tsensor"; reg = <0x00 0xfa0d0000 0x00 0x10000 0x00 0xfa0a0000 0x00 0x10000>; sensor_id = <0x00>; sensor_name = "tsensor0"; status = "okay"; force_init = <0x00>; trim_mode = <0x00>; low_thld = <0x00>; high_thld = <0x0f>; ultra_high_thld = <0x3ff>; sample_num = <0x00>; }; tsensor@FA0E0000 { compatible = "tsensor"; reg = <0x00 0xfa0e0000 0x00 0x10000 0x00 0xfa0a0000 0x00 0x10000>; sensor_id = <0x01>; sensor_name = "tsensor1"; status = "okay"; force_init = <0x00>; trim_mode = <0x00>; low_thld = <0x00>; high_thld = <0x0f>; ultra_high_thld = <0x3ff>; sample_num = <0x00>; }; memory@0 { device_type = "memory"; reg = <0x0 0x00000000 0x0 0x1A500000>, <0x0 0x20000000 0x0 0xA0000000>, <0x4 0xC0000000 0x1 0x40000000>; }; };
10-23
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