module test(
input wire clk ,
input wire btn,
output reg[1:0] CMD
);
reg btn_sync_1;
reg btn_sync_2;
reg btn_prev;
reg state = 1;
always @(posedge clk) begin
btn_sync_1 <= btn;
btn_sync_2 <= btn_sync_1;
end
wire btn_pressed = ~btn_sync_2 && btn_prev;
always @(posedge clk) begin
btn_prev <= btn_sync_2;
end
always @(posedge clk) begin
if (btn_pressed) begin
state <= ~state;
end
end
always @(posedge clk) begin
if(state)begin
end else begin
end
end
按钮波形
+----+
| |
-----------+ +--------------------------------- btn_sync_1
+----+
| |
-------------+ +------------------------------- btn_sync_2
+----+
| |
--------------+ +------------------------------ btn_prev
++
||
------------------++------------------------------ btn_pressed