紧急拨号之----T911需求

在E911 CSFB呼叫期间,即使UE移动到不同位置区,也应能成功收发短信。分析发现,当LTE的TAI与WCDMA的LAC不匹配时,UE应执行位置更新(LU)。但实际情况中,由于M*平台未按协议执行LU,导致MM状态为NOT_UPDATED,从而无法建立MM连接发送短信。解决方案涉及修改SBP文件以触发LU。

Issue Description:

During an E911 CSFB Call, UE should successfully send and receive text messages (to PSAP and other users) even if UE moves to a different Location Area during CSFB establishment. 

show Log Analysis:

查看log,发现LTE下的TAI与WCDMA下的LAC不一样,也就是说CSFB到WCDMA后,UE应该会执行LU , 查看最新的协议TS23.272 :

When the target RAT for emergency call due to CSFB is selected based on cell re-selection or redirection by the network and the UE moves to a different LA then it is possible that the UE continues the emergency call setup without performing a location updating procedure. In this case, the UE performs the emergency call setup with IMSI NOTE 2:

这里是说手机是可以不进行LU ,但是有个前提是emergency call setup with imsi note2 ,再来看协议,发现这种情况是说的是

说的3G下没有PS业务的情况下才可以不进行LU.

继续看协议:

查看6.2章节说明:

Warning (14284): Synthesized away the following node(s): Warning (14285): Synthesized away the following RAM node(s): Warning (14320): Synthesized away node "ONE_PORT_RAM_16X2048:ONE_PORT_RAM_16X2048|RAM0:RAM0_inst|altsyncram:altsyncram_component|altsyncram_57g1:auto_generated|q_a[0]" Warning (14320): Synthesized away node "ONE_PORT_RAM_16X2048:ONE_PORT_RAM_16X2048|RAM0:RAM0_inst|altsyncram:altsyncram_component|altsyncram_57g1:auto_generated|q_a[1]" Warning (14320): Synthesized away node "ONE_PORT_RAM_16X2048:ONE_PORT_RAM_16X2048|RAM0:RAM0_inst|altsyncram:altsyncram_component|altsyncram_57g1:auto_generated|q_a[2]" Warning (14320): Synthesized away node "ONE_PORT_RAM_16X2048:ONE_PORT_RAM_16X2048|RAM0:RAM0_inst|altsyncram:altsyncram_component|altsyncram_57g1:auto_generated|q_a[3]" Warning (14320): Synthesized away node "ONE_PORT_RAM_16X2048:ONE_PORT_RAM_16X2048|RAM0:RAM0_inst|altsyncram:altsyncram_component|altsyncram_57g1:auto_generated|q_a[4]" Warning (14320): Synthesized away node "ONE_PORT_RAM_16X2048:ONE_PORT_RAM_16X2048|RAM0:RAM0_inst|altsyncram:altsyncram_component|altsyncram_57g1:auto_generated|q_a[5]" Warning (14320): Synthesized away node "ONE_PORT_RAM_16X2048:ONE_PORT_RAM_16X2048|RAM0:RAM0_inst|altsyncram:altsyncram_component|altsyncram_57g1:auto_generated|q_a[6]" Warning (14320): Synthesized away node "ONE_PORT_RAM_16X2048:ONE_PORT_RAM_16X2048|RAM0:RAM0_inst|altsyncram:altsyncram_component|altsyncram_57g1:auto_generated|q_a[7]" Warning (14320): Synthesized away node "ONE_PORT_RAM_16X2048:ONE_PORT_RAM_16X2048|RAM0:RAM0_inst|altsyncram:altsyncram_component|altsyncram_57g1:auto_generated|q_a[8]" Warning (14320): Synthesized away node "ONE_PORT_RAM_16X2048:ONE_PORT_RAM_16X2048|RAM0:RAM0_inst|altsyncram:altsyncram_component|altsyncram_57g1:auto_generated|q_a[9]" Warning (14320): Synthesized away node "ONE_PORT_RAM_16X2048:ONE_PORT_RAM_16X2048|RAM0:RAM0_inst|altsyncram:altsyncram_component|altsyncram_57g1:auto_generated|q_a[10]" Warning (14320): Synthesized away node "ONE_PORT_RAM_16X2048:ONE_PORT_RAM_16X2048|RAM0:RAM0_inst|altsyncram:altsyncram_component|altsyncram_57g1:auto_generated|q_a[11]" Warning (14320): Synthesized away node "ONE_PORT_RAM_16X2048:ONE_PORT_RAM_16X2048|RAM0:RAM0_inst|altsyncram:altsyncram_component|altsyncram_57g1:auto_generated|q_a[12]" Warning (14320): Synthesized away node "ONE_PORT_RAM_16X2048:ONE_PORT_RAM_16X2048|RAM0:RAM0_inst|altsyncram:altsyncram_component|altsyncram_57g1:auto_generated|q_a[13]" Warning (14320): Synthesized away node "ONE_PORT_RAM_16X2048:ONE_PORT_RAM_16X2048|RAM0:RAM0_inst|altsyncram:altsyncram_component|altsyncram_57g1:auto_generated|q_a[14]" Warning (14320): Synthesized away node "ONE_PORT_RAM_16X2048:ONE_PORT_RAM_16X2048|RAM0:RAM0_inst|altsyncram:altsyncram_component|altsyncram_57g1:auto_generated|q_a[15]" Warning (14320): Synthesized away node "FIFO_16X2048:FIFO_16X2048|FIFO_16_2048:FIFO_16_2048_inst|scfifo:scfifo_component|scfifo_nq31:auto_generated|a_dpfifo_u041:dpfifo|dpram_t911:FIFOram|altsyncram_e6k1:altsyncram1|q_b[0]" Warning (14320): Synthesized away node "FIFO_16X2048:FIFO_16X2048|FIFO_16_2048:FIFO_16_2048_inst|scfifo:scfifo_component|scfifo_nq31:auto_generated|a_dpfifo_u041:dpfifo|dpram_t911:FIFOram|altsyncram_e6k1:altsyncram1|q_b[1]" Warning (14320): Synthesized away node "FIFO_16X2048:FIFO_16X2048|FIFO_16_2048:FIFO_16_2048_inst|scfifo:scfifo_component|scfifo_nq31:auto_generated|a_dpfifo_u041:dpfifo|dpram_t911:FIFOram|altsyncram_e6k1:altsyncram1|q_b[2]" Warning (14320): Synthesized away node "FIFO_16X2048:FIFO_16X2048|FIFO_16_2048:FIFO_16_2048_inst|scfifo:scfifo_component|scfifo_nq31:auto_generated|a_dpfifo_u041:dpfifo|dpram_t911:FIFOram|altsyncram_e6k1:altsyncram1|q_b[3]" Warning (14320): Synthesized away node "FIFO_16X2048:FIFO_16X2048|FIFO_16_2048:FIFO_16_2048_inst|scfifo:scfifo_component|scfifo_nq31:auto_generated|a_dpfifo_u041:dpfifo|dpram_t911:FIFOram|altsyncram_e6k1:altsyncram1|q_b[4]" Warning (14320): Synthesized away node "FIFO_16X2048:FIFO_16X2048|FIFO_16_2048:FIFO_16_2048_inst|scfifo:scfifo_component|scfifo_nq31:auto_generated|a_dpfifo_u041:dpfifo|dpram_t911:FIFOram|altsyncram_e6k1:altsyncram1|q_b[5]" Warning (14320): Synthesized away node "FIFO_16X2048:FIFO_16X2048|FIFO_16_2048:FIFO_16_2048_inst|scfifo:scfifo_component|scfifo_nq31:auto_generated|a_dpfifo_u041:dpfifo|dpram_t911:FIFOram|altsyncram_e6k1:altsyncram1|q_b[6]" Warning (14320): Synthesized away node "FIFO_16X2048:FIFO_16X2048|FIFO_16_2048:FIFO_16_2048_inst|scfifo:scfifo_component|scfifo_nq31:auto_generated|a_dpfifo_u041:dpfifo|dpram_t911:FIFOram|altsyncram_e6k1:altsyncram1|q_b[7]" Warning (14320): Synthesized away node "FIFO_16X2048:FIFO_16X2048|FIFO_16_2048:FIFO_16_2048_inst|scfifo:scfifo_component|scfifo_nq31:auto_generated|a_dpfifo_u041:dpfifo|dpram_t911:FIFOram|altsyncram_e6k1:altsyncram1|q_b[8]" Warning (14320): Synthesized away node "FIFO_16X2048:FIFO_16X2048|FIFO_16_2048:FIFO_16_2048_inst|scfifo:scfifo_component|scfifo_nq31:auto_generated|a_dpfifo_u041:dpfifo|dpram_t911:FIFOram|altsyncram_e6k1:altsyncram1|q_b[9]" Warning (14320): Synthesized away node "FIFO_16X2048:FIFO_16X2048|FIFO_16_2048:FIFO_16_2048_inst|scfifo:scfifo_component|scfifo_nq31:auto_generated|a_dpfifo_u041:dpfifo|dpram_t911:FIFOram|altsyncram_e6k1:altsyncram1|q_b[10]" Warning (14320): Synthesized away node "FIFO_16X2048:FIFO_16X2048|FIFO_16_2048:FIFO_16_2048_inst|scfifo:scfifo_component|scfifo_nq31:auto_generated|a_dpfifo_u041:dpfifo|dpram_t911:FIFOram|altsyncram_e6k1:altsyncram1|q_b[11]" Warning (14320): Synthesized away node "FIFO_16X2048:FIFO_16X2048|FIFO_16_2048:FIFO_16_2048_inst|scfifo:scfifo_component|scfifo_nq31:auto_generated|a_dpfifo_u041:dpfifo|dpram_t911:FIFOram|altsyncram_e6k1:altsyncram1|q_b[12]" Warning (14320): Synthesized away node "FIFO_16X2048:FIFO_16X2048|FIFO_16_2048:FIFO_16_2048_inst|scfifo:scfifo_component|scfifo_nq31:auto_generated|a_dpfifo_u041:dpfifo|dpram_t911:FIFOram|altsyncram_e6k1:altsyncram1|q_b[13]" Warning (14320): Synthesized away node "FIFO_16X2048:FIFO_16X2048|FIFO_16_2048:FIFO_16_2048_inst|scfifo:scfifo_component|scfifo_nq31:auto_generated|a_dpfifo_u041:dpfifo|dpram_t911:FIFOram|altsyncram_e6k1:altsyncram1|q_b[14]" Warning (14320): Synthesized away node "FIFO_16X2048:FIFO_16X2048|FIFO_16_2048:FIFO_16_2048_inst|scfifo:scfifo_component|scfifo_nq31:auto_generated|a_dpfifo_u041:dpfifo|dpram_t911:FIFOram|altsyncram_e6k1:altsyncram1|q_b[15]" Warning (12241): 3 hierarchies have connectivity warnings - see the Connectivity Checks report folder
09-29
你遇到的警告信息来自 **Intel Quartus Prime** 综合工具,属于 FPGA 设计流程中的综合(Synthesis)阶段。我们来逐条分析这些警告,并给出解决方案。 --- ### ❗ 警告解释 #### 🔹 `Warning (14284): Synthesized away the following node(s):` #### 🔹 `Warning (14285): Synthesized away the following RAM node(s):` 这表示 Quartus 在综合过程中 **移除了某些 RAM 节点**。也就是说,你设计中定义的 RAM 模块(如 `altsyncram` 或 `scfifo`)被“优化掉”了,没有实际生成硬件资源。 #### 🔹 `Warning (14320): Synthesized away node "..."` 具体列出了哪些信号或节点被移除,例如: ``` ONE_PORT_RAM_16X2048:ONE_PORT_RAM_16X2048|RAM0:RAM0_inst|... ``` 说明你的单端口 RAM 实例 FIFO 内部使用的双口 RAM 都被综合掉了。 --- ### 🚩 常见原因 RAM/FIFO 被“synthesized away”的主要原因如下: 1. **未连接输出端口(q)** - 如果 RAM 的读出数据线 `q[]` 没有连接到任何逻辑,Quartus 会认为该 RAM 是无用的,从而将其删除。 2. **写使能(wren)始终为低 / 地址/数据未驱动** - 若写使能信号恒为 0,或者地址、数据输入未被赋值,则整个 RAM 不会被访问 → 被优化。 3. **FIFO 输出未使用** - 类似地,如果 FIFO 的 `q`, `empty`, `full` 等输出未被后续逻辑使用,也会被移除。 4. **复位期间初始化问题或编译选项限制** - 某些配置下,若 RAM 初始化文件(.mif)加载失败或路径错误,也可能导致实例化失败。 5. **仿真模型与综合模型不一致** - 使用了行为级描述但未正确调用 IP 核。 --- ### ✅ 解决方案 #### ✅ 检查 RAM FIFO 的连接是否完整 以你使用的 `ONE_PORT_RAM_16X2048` `FIFO_16X2048` 为例,确保以下关键信号都已正确连接: ##### 示例:One-Port RAM 连接检查(Altera/Intel altsyncram) ```verilog // 示例:正确实例化的单端口 RAM module ONE_PORT_RAM_16X2048 ( input clock, input wren, input [11:0] address, // 2048 = 2^11 -> 11 bits; maybe 12? input [15:0] data, output reg[15:0] q ); altsyncram #( .width_a(16), .widthad_a(11), // 地址宽度 .numwords_a(2048), .operation_mode("SINGLE_PORT"), .outdata_reg_a("UNREGISTERED"), // 注意寄存器设置 .init_file(""), // 可选初始化文件 .read_during_write_mode_a("NEW_DATA_NO_NBE_READ") ) RAM0_inst ( .clock0(clock), .wren_a(wren), .address_a(address), .data_a(data), .q_a(q) ); // ⚠️ 必须在顶层设计中使用 q!否则会被优化掉 endmodule ``` > 💡 关键点:`q` 输出必须连接到其他模块或顶层输出端口! #### ✅ 检查 FIFO 使用情况 如果你用了 `scfifo`,要确认: - `q` 是否连接? - `empty` 是否用于控制读取? - `full` 是否用于控制写入? 示例片段: ```verilog wire [15:0] fifo_out; wire fifo_empty, fifo_full; FIFO_16X2048 your_fifo_inst ( .data(data_in), .wrreq(wr_req), .rdreq(rd_req), .clock(clk), .q(fifo_out), .empty(fifo_empty), .full(fifo_full) ); // 必须使用 fifo_out,比如驱动 LED 或发送给其他模块 assign some_output = fifo_out; // 即使只是测试也要用! ``` #### ✅ 强制保留信号(防止优化) 如果只是为了调试而想保留 RAM/FIFO,即使未使用其输出,可用 `(* keep *)` 属性阻止优化: ```verilog output [15:0] q; reg [15:0] q /* synthesis keep */; // 或者用综合指令保留整个模块/信号 // synthesis read_comments_as_HDL on // (* keep *) wire [15:0] q_debug = q_a; ``` 也可以在 Quartus 设置中关闭 RAM 移除优化: #### ✅ Quartus 设置:禁止移除未使用模块 进入: ``` Assignments → Settings → Compiler Settings → Advanced Settings (Synthesis) → Remove unreferenced signals: 设置为 "None" ``` 或者添加 `.qsf` 配置: ```tcl set_global_assignment -name SYNTHESIS_EFFORT STANDARD set_global_assignment -name OPTIMIZATION_MODE "BALANCED" set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS OFF ``` #### ✅ 检查 MIF 文件路径(如有初始化需求) 如果 RAM 应从 `.mif` 文件初始化,请确保: - `.mif` 文件在项目目录中 - 路径正确(相对或绝对) - 在 IP 参数中指定 `.mif` 名称 --- ### ✅ 如何验证 RAM 是否真正生成? 查看: ``` Compilation Report → Analysis & Synthesis → Entity Hierarchies → 查看是否有 ram_block 或 altsyncram 实例存在 ``` 或者: ``` Fitter → Resource Section → Memory Summary ``` 应显示 MLAB 或 M20K 块的使用数量。 如果没有出现,说明 RAM 真的没生成。 --- ### ✅ 总结解决步骤 | 步骤 | 操作 | |------|------| | 1 | 检查 RAM/FIFO 所有 I/O 是否连接,尤其是输出 `q` | | 2 | 确保 `wren`, `rdreq`, `wrreq` 等控制信号不是常量 | | 3 | 在顶层设计中“使用” RAM/FIFO 的输出(哪怕只是 assign 到一个 wire) | | 4 | 添加 `/* synthesis keep */` 属性防止优化 | | 5 | 修改 Quartus 设置禁用自动移除 | | 6 | 检查 `.mif` 文件是否存在且路径正确 | | 7 | 编译后查看 Resource Usage 报告确认 RAM 是否生成 | --- ###
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