【MCP PL-600功能测试全解析】:掌握核心测试技巧,提升系统验证效率

第一章:MCP PL-600功能测试概述

MCP PL-600是一款面向工业自动化控制场景的多功能通信处理器,具备强大的协议转换、数据采集与边缘计算能力。其功能测试旨在验证设备在真实部署环境下的稳定性、兼容性及响应性能,确保系统集成的可靠性。

测试目标

  • 验证MCP PL-600与主流PLC设备的通信兼容性
  • 评估多协议并发处理能力(如Modbus TCP、Profinet、EtherNet/IP)
  • 测试断线重连机制与数据缓存恢复功能
  • 确认固件升级过程中的系统鲁棒性

测试环境配置

项目配置说明
设备型号MCP PL-600 v2.1
测试主机Windows 11, 16GB RAM, Intel i7
网络环境千兆局域网,延迟控制在1ms以内
配套工具Wireshark、Postman、Modbus Slave仿真器

基础通信测试代码示例

// Go语言模拟Modbus TCP客户端请求
package main

import (
	"fmt"
	"github.com/goburrow/modbus"
)

func main() {
	// 连接到MCP PL-600的Modbus服务端(IP: 192.168.1.60, 端口: 502)
	handler := modbus.NewTCPClientHandler("192.168.1.60:502")
	handler.Timeout = 5

	if err := handler.Connect(); err != nil {
		fmt.Println("连接失败:", err)
		return
	}
	defer handler.Close()

	client := modbus.NewClient(handler)
	result, err := client.ReadHoldingRegisters(0, 4) // 读取前4个寄存器
	if err != nil {
		fmt.Println("读取失败:", err)
	} else {
		fmt.Printf("寄存器数据: %v\n", result)
	}
}
graph TD A[启动MCP PL-600] --> B[加载通信协议栈] B --> C{是否检测到异常?} C -->|是| D[记录日志并告警] C -->|否| E[进入正常工作模式] E --> F[周期性发送心跳包]

第二章:MCP PL-600测试环境构建与配置

2.1 理解MCP PL-600系统架构与测试边界

MCP PL-600系统采用分层架构设计,包含接口层、业务逻辑层与数据处理层,支持高并发场景下的稳定运行。各层之间通过明确定义的API契约通信,确保模块解耦。
核心组件交互
系统主要由控制总线、任务调度器和状态监控模块构成,协同完成指令下发与反馈采集。
测试边界定义
测试覆盖单元测试(覆盖率≥85%)、集成测试与端到端流程验证,但不包括第三方硬件可靠性验证。
// 示例:任务状态检查接口
func CheckTaskStatus(taskID string) (*Task, error) {
    if taskID == "" {
        return nil, errors.New("taskID不能为空")
    }
    // 从状态缓存中获取任务信息
    task := cache.Get(taskID)
    return task, nil
}
该函数实现任务状态查询,参数taskID用于唯一标识任务,返回结构体指针与错误类型,适用于异步任务轮询场景。

2.2 搭建高保真测试环境的实践方法

容器化环境的一致性构建
使用 Docker 构建标准化测试环境,确保开发、测试与生产环境高度一致。通过 Dockerfile 定义运行时依赖:
FROM openjdk:11-jre-slim
COPY app.jar /app/app.jar
ENV SPRING_PROFILES_ACTIVE=test
EXPOSE 8080
CMD ["java", "-jar", "/app/app.jar"]
该配置指定 Java 运行环境,注入测试配置文件,并暴露标准端口,实现环境可复制。
数据同步机制
采用数据库快照与脱敏同步策略,保障测试数据真实性与安全性。定期从生产环境导出结构化数据,经匿名化处理后导入测试库。
步骤操作工具示例
1数据抽取mysqldump + WHERE 条件过滤
2字段脱敏Python 脚本替换敏感字段
3导入测试库MySQL CLI 批量导入

2.3 测试数据准备与仿真设备集成

在自动化测试流程中,高质量的测试数据是验证系统稳定性的基础。为确保测试覆盖全面,需构建包含正常值、边界值和异常值的数据集,并通过脚本自动注入至仿真环境。
仿真设备数据注入示例
# 模拟传感器数据生成
import random
def generate_sensor_data(count):
    return [{"id": i, "temp": round(random.uniform(15, 35), 2),
             "status": "OK" if random.random() > 0.1 else "FAULT"}
            for i in range(count)]
该函数生成包含设备ID、温度读数和状态标记的测试数据列表,模拟真实传感器输出。随机生成的故障率约为10%,用于验证系统容错能力。
设备集成流程

测试系统 ←→ 数据注入模块 ←→ 仿真设备集群

通过标准化接口协议(如MQTT/Modbus),实现测试平台与仿真设备间的双向通信,确保指令与反馈同步。

2.4 接口通信协议配置与验证技巧

在接口通信中,正确配置协议参数是确保系统间稳定交互的基础。常见的通信协议如HTTP/HTTPS、gRPC、MQTT等,需根据场景选择合适的传输机制。
协议配置关键参数
  • 超时设置:避免请求长期挂起,建议设置连接超时(connectTimeout)和读写超时(readTimeout)
  • 重试机制:网络抖动时自动恢复,建议配合指数退避策略
  • 序列化格式:优先使用JSON或Protobuf以提升解析效率
验证接口连通性示例
curl -X POST http://api.example.com/v1/data \
  -H "Content-Type: application/json" \
  -d '{"id": 123}' \
  --max-time 10
该命令通过 curl 发起 POST 请求,--max-time 10 限制总耗时不超过10秒,防止阻塞。响应状态码和返回体可用于判断服务可用性。
常见错误码对照表
状态码含义处理建议
401未授权检查Token有效性
429请求过频启用限流退避
503服务不可用触发健康检查流程

2.5 测试工具链选型与自动化平台对接

在构建高效稳定的测试体系时,工具链的合理选型至关重要。综合项目技术栈与团队协作模式,最终选定 **Postman** 用于接口测试、**Selenium** 实现UI自动化、**Jest** 承担单元测试任务,并通过 **Jenkins** 实现持续集成。
主流测试工具对比
工具适用场景集成难度维护成本
PostmanAPI测试
SeleniumWeb UI自动化
Jest前端单元测试
自动化平台对接示例

// Jenkinsfile 中定义的自动化流水线
pipeline {
  agent any
  stages {
    stage('Test') {
      steps {
        sh 'npm run test:unit'   // 执行 Jest 单元测试
        sh 'newman run collection.json' // 运行 Postman 集合
      }
    }
  }
}
该脚本定义了CI流程中的测试阶段,通过调用 npm 和 Newman 命令分别触发前端单元测试与接口自动化测试,实现与Jenkins平台的无缝对接。

第三章:核心功能测试用例设计

3.1 基于需求规格的功能路径覆盖策略

在功能测试设计中,基于需求规格的功能路径覆盖策略旨在通过分析系统功能流程图,识别关键执行路径,确保每个业务逻辑分支均被测试覆盖。
路径建模与需求映射
将需求文档中的业务流程转化为控制流图(CFG),每个节点代表一个操作步骤,边表示状态转移。例如,用户登录流程可建模为:
开始 → 输入凭证 → 验证身份 → [成功] → 主界面           └→ [失败] → 提示错误
覆盖规则实现
使用代码标注关键路径断言,提升可追踪性:

// 标记登录成功路径
func TestLogin_SuccessPath(t *testing.T) {
    user := Login("valid_user", "pass123")
    if user.Session == nil {
        t.Error("预期会话创建,实际未生成") // 覆盖失败路径
    }
}
该测试用例明确对应“验证身份→主界面”的成功路径,参数需符合有效凭证组合。
  • 每条独立业务路径至少对应一个测试用例
  • 边界值输入应触发异常路径执行

3.2 关键控制逻辑的边界值与异常场景设计

在构建高可靠系统时,关键控制逻辑必须覆盖边界条件与异常路径。仅验证正常流程无法保障生产环境下的稳定性,需主动设计极端输入与状态跃迁场景。
边界值分析示例
以分页查询为例,页码与大小的合法范围需明确处理:
// 处理分页参数的边界校正
func adjustPage(page, size int) (int, int) {
    if page < 1 {
        page = 1  // 最小页码为1
    }
    if size < 1 {
        size = 10 // 默认每页大小
    } else if size > 100 {
        size = 100 // 最大限制100
    }
    return page, size
}
该函数确保输入参数始终落在有效区间 [1,100] 内,防止数据库扫描过载或空结果集攻击。
常见异常场景分类
  • 输入为空或为零值
  • 并发修改导致状态冲突
  • 外部依赖超时或返回错误
  • 资源耗尽(如内存、连接池)

3.3 多工况组合测试的高效实现方法

在复杂系统测试中,多工况组合测试面临用例爆炸问题。为提升效率,可采用基于正交实验设计的测试用例生成策略,有效减少冗余组合。
正交表驱动的测试设计
通过正交表将多因素多水平的测试组合压缩至代表性子集。例如三因素三水平问题,传统全量组合需27组,而正交法仅需9组:
工况A工况B工况C
111
122
133
212
223
231
313
321
332
自动化执行框架示例

func RunCombinationTests(configs []TestCase) {
    for _, tc := range configs {
        t.Run(tc.Name, func(t *testing.T) {
            result := ExecuteWorkload(tc.Params)
            assert.Equal(t, tc.Expectation, result.Status)
        })
    }
}
该代码段定义了并行执行多工况测试的框架,TestCase 结构封装参数与预期结果,ExecuteWorkload 模拟实际业务负载调用,断言确保输出符合预期。

第四章:典型应用场景下的测试执行

4.1 启动自检与运行模式切换功能验证

系统上电后首先执行启动自检(Power-On Self-Test, POST),检测关键硬件模块的可用性。自检流程涵盖内存、存储、通信接口等核心组件,确保运行环境安全可靠。
自检阶段关键操作
  • 初始化看门狗定时器
  • 校验固件完整性(CRC32)
  • 检测外部传感器连接状态
运行模式切换逻辑
系统根据启动引脚电平决定运行模式:

// 模式检测代码片段
if (GPIO_READ(MODE_PIN) == HIGH) {
    enter_normal_mode();   // 正常运行模式
} else {
    enter_recovery_mode(); // 恢复模式,用于固件升级
}
上述代码在启动引导程序中执行,MODE_PIN为外部拨码开关控制,高电平触发正常流程,否则进入恢复模式,便于现场维护。
验证结果记录
测试项预期结果实际结果
自检通过LED绿灯常亮符合
进入恢复模式串口输出 recovery prompt符合

4.2 故障注入与系统容错能力实测分析

在分布式系统中,验证系统的容错能力是保障高可用性的关键环节。通过主动引入故障,可以评估系统在异常条件下的行为表现。
故障注入策略设计
采用Chaos Engineering原则,模拟网络延迟、服务中断和节点宕机等场景。常用工具如Chaos Mesh支持声明式故障定义:

apiVersion: chaos-mesh.org/v1alpha1
kind: NetworkChaos
metadata:
  name: delay-pod
spec:
  action: delay
  mode: one
  selector:
    labelSelectors:
      "app": "payment-service"
  delay:
    latency: "500ms"
    correlation: "100"
上述配置对标签为app=payment-service的Pod注入500ms固定延迟,用于测试调用链超时容忍度。
容错能力评估指标
通过以下维度量化系统韧性:
  • 请求成功率:故障期间P99成功率不低于95%
  • 自动恢复时间:从故障发生到服务恢复正常小于30秒
  • 数据一致性:无丢失或重复写入

4.3 实时响应性能与指令执行精度评估

实时性指标测量方法
为评估系统在高并发场景下的响应能力,采用微秒级时间戳记录指令从接收至执行完成的全过程。通过内核态计时器采集端到端延迟,并统计百分位延迟(P50、P95、P99)以反映系统稳定性。
// 示例:Go语言中使用time包测量指令执行耗时
start := time.Now()
executeCommand(cmd)
latency := time.Since(start)
log.Printf("指令 %s 执行耗时: %vμs", cmd.ID, latency.Microseconds())
上述代码通过time.Since精确计算指令执行间隔,结合日志系统实现性能追踪。微秒级精度确保对实时性变化敏感。
执行精度验证机制
建立指令校验流水线,对比预期输出与实际执行结果。采用如下误差分类标准进行量化评估:
误差等级偏差范围可接受性
A< 0.5%合格
B0.5%–1.0%警告
C> 1.0%失败

4.4 多系统协同工作下的交互一致性测试

在分布式架构中,多个子系统间的数据交互频繁且复杂,保障交互一致性成为关键挑战。需通过统一协议与校验机制确保操作的原子性与结果一致性。
数据同步机制
采用事件驱动模型实现异步解耦,结合消息队列确保事件传递可靠:

// 发布订单创建事件
event := &OrderEvent{
    OrderID:    "1001",
    Status:     "created",
    Timestamp:  time.Now().Unix(),
}
err := eventBus.Publish("order.created", event)
if err != nil {
    log.Errorf("发布事件失败: %v", err)
}
该代码将订单事件发布至消息总线,下游系统订阅后执行对应逻辑,保证状态变更可追溯。
一致性验证策略
  • 基于幂等性的重试机制,防止重复操作破坏一致性
  • 引入对账服务定期比对各系统关键状态
  • 使用分布式追踪定位跨系统调用链中的异常节点

第五章:测试总结与效率优化建议

关键性能瓶颈识别
在多个迭代周期中,API 响应延迟主要集中在数据库查询阶段。通过引入 pprof 进行性能剖析,发现未加索引的模糊搜索操作占用了 68% 的请求耗时。

// 示例:优化前的低效查询
rows, err := db.Query("SELECT * FROM logs WHERE message LIKE ?", "%error%")

// 优化后:使用全文索引 + 分页
rows, err := db.Query("SELECT id, message FROM logs WHERE MATCH(message) AGAINST(? IN BOOLEAN MODE) LIMIT 100", "error")
自动化测试流程重构
采用分层测试策略显著提升 CI/CD 效率。以下为当前测试任务分布:
测试类型执行频率平均耗时并行节点数
单元测试每次提交2.1 min4
集成测试每日构建12.5 min2
E2E 测试版本发布前23 min3
资源利用率优化方案
  • 将测试环境数据库从独占实例改为容器化部署,资源占用下降 40%
  • 引入测试数据生命周期管理,自动清理 7 天前的临时数据
  • 使用 Ginkgo 的并行测试能力,在 8 核环境中缩短执行时间至原来的 37%

优化后测试流水线:

代码提交 → 单元测试(并行)→ 构建镜像 → 部署沙箱 → 集成测试 → 报告生成

↑______________________← 自动回滚机制 ←

PL fatal error... [2025-09-14 14:15:23.977] [2025-09-14 14:15:23.977] PL delay for Long Press Reboot [2025-09-14 14:15:23.977] [2025-09-14 14:15:23.977] [PLFM] emergency download mode(timeout: 5s). [2025-09-14 14:15:23.977] [2025-09-14 14:15:23.977] [RGU] mtk_arch_reset at pre-loader! [2025-09-14 14:15:23.977] [2025-09-14 14:15:23.977] [RGU] disable pwrap before WDT [2025-09-14 14:15:23.977] [2025-09-14 14:15:23.977] [RGU] pmic do nothing [2025-09-14 14:15:23.977] [2025-09-14 14:15:23.977] [RGU] mtk_wdt_reset WDT MODE=25 [2025-09-14 14:15:23.977] [2025-09-14 14:15:24.108] sPL_LOG_STORE: check once, sig value 0x1800, addr 0x102180. [2025-09-14 14:15:24.108] [2025-09-14 14:15:24.108] PL_LOG_STORE:sram->sig value 0xABCD1234! [2025-09-14 14:15:24.108] [2025-09-14 14:15:24.108] ramrom delsel: 0x06C4E4F3 [2025-09-14 14:15:24.108] [2025-09-14 14:15:24.108] bandgap ref vol: 0x302012A8 [2025-09-14 14:15:24.108] [2025-09-14 14:15:24.108] Pll init start... [2025-09-14 14:15:24.108] [2025-09-14 14:15:24.108] Pll init Done! [2025-09-14 14:15:24.108] [2025-09-14 14:15:24.108] [RGU] rst from: pl [2025-09-14 14:15:24.108] [2025-09-14 14:15:24.108] [RGU] MODE: 0x25 [2025-09-14 14:15:24.108] [2025-09-14 14:15:24.108] [RGU] STA: 0x40000000 [2025-09-14 14:15:24.108] [2025-09-14 14:15:24.108] [RGU] LENGTH: 0xFFE0 [2025-09-14 14:15:24.108] [2025-09-14 14:15:24.108] [RGU] INTERVAL: 0xFFF [2025-09-14 14:15:24.108] [2025-09-14 14:15:24.108] [RGU] SWSYSRST: 0x8000 [2025-09-14 14:15:24.108] [2025-09-14 14:15:24.108] [RGU] LATCH_CTL: 0x21E71 [2025-09-14 14:15:24.108] [2025-09-14 14:15:24.108] [RGU] NONRST_REG: 0x40000000 [2025-09-14 14:15:24.108] [2025-09-14 14:15:24.108] [RGU] NONRST_REG2: 0x24002000 [2025-09-14 14:15:24.140] [2025-09-14 14:15:24.140] [RGU] DEBUG_CTL: 0x200F1 [2025-09-14 14:15:24.140] [2025-09-14 14:15:24.140] [RGU] parse g_rgu_status: 2 (0x2) [2025-09-14 14:15:24.140] [2025-09-14 14:15:24.140] [RGU] Set NONRST_REG to 0x40000000 [2025-09-14 14:15:24.140] [2025-09-14 14:15:24.140] [RGU] mtk_wdt_mode_config mode value=30, tmp:22000030 [2025-09-14 14:15:24.140] [2025-09-14 14:15:24.140] [RGU] mtk_wdt_mode_config mode value=7D, tmp:2200007D [2025-09-14 14:15:24.140] [2025-09-14 14:15:24.140] [RGU] mtk_wdt_reset_deglitch_enable: MTK_WDT_RSTDEG_EN1(8000A357), MTK_WDT_RSTDEG_EN2(800067D2) [2025-09-14 14:15:24.140] [2025-09-14 14:15:24.140] [RGU] rgu_update_reg: 0, bits: 0xC000, addr: 0x10007040, val: 0x200F1 [2025-09-14 14:15:24.140] [2025-09-14 14:15:24.140] [RGU] rgu_update_reg: 0, bits: 0x300, addr: 0x100070A0, val: 0xFF [2025-09-14 14:15:24.140] [2025-09-14 14:15:24.140] [RGU] mtk_wdt_pre_init: MTK_WDT_DEBUG_CTL(0x200F1) [2025-09-14 14:15:24.140] [2025-09-14 14:15:24.140] [RGU] mtk_wdt_pre_init: MTK_WDT_DEBUG_CTL2(0xFF) [2025-09-14 14:15:24.140] [2025-09-14 14:15:24.140] [RGU] mtk_wdt_pre_init: MTK_WDT_LATCH_CTL(0x21E71) [2025-09-14 14:15:24.140] [2025-09-14 14:15:24.140] [RGU] mtk_wdt_pre_init: MTK_WDT_REQ_MODE(3F0032), MTK_WDT_REQ_IRQ_EN(3F0032) [2025-09-14 14:15:24.140] [2025-09-14 14:15:24.140] [PWRAP] si_en_sel = 0, si_ck_sel = 0, si_sample_ctrl = 0, rdata = 96A9 [2025-09-14 14:15:24.140] [2025-09-14 14:15:24.140] [PWRAP] si_en_sel = 0, si_ck_sel = 1, si_sample_ctrl = 20, rdata = 5AA5, Pass [2025-09-14 14:15:24.140] [2025-09-14 14:15:24.140] [PWRAP] InitSiStrobe (7, 7, DA65) Data Boundary Is Found !! [2025-09-14 14:15:24.140] [2025-09-14 14:15:24.140] [PWRAP] SI Strobe Calibration For PMIC 0 Done, (40, 7) [2025-09-14 14:15:24.140] [2025-09-14 14:15:24.140] [PWRAP] Read Test pass, return_value=0x0 [2025-09-14 14:15:24.173] [2025-09-14 14:15:24.173] [PWRAP] Write Test pass [2025-09-14 14:15:24.173] [2025-09-14 14:15:24.173] [PWRAP] RECORD_CMD0: 0x152A (Last one command addr) [2025-09-14 14:15:24.173] [2025-09-14 14:15:24.173] [PWRAP] RECORD_WDATA0:0x2D (Last one command wdata) [2025-09-14 14:15:24.173] [2025-09-14 14:15:24.173] [PWRAP] RECORD_CMD1: 0x196C (Last second command addr) [2025-09-14 14:15:24.173] [2025-09-14 14:15:24.173] [PWRAP] RECORD_WDATA1:0x0 (Last second command wdata) [2025-09-14 14:15:24.173] [2025-09-14 14:15:24.173] [PWRAP] RECORD_CMD2: 0x170E (Last third command addr) [2025-09-14 14:15:24.173] [2025-09-14 14:15:24.173] [PWRAP] RECORD_WDATA2:0x7A (Last third command wdata) [2025-09-14 14:15:24.173] [2025-09-14 14:15:24.173] [PWRAP] init pass, ret=0. [2025-09-14 14:15:24.173] [2025-09-14 14:15:24.173] [2025-09-14 14:15:24.173] [2025-09-14 14:15:24.173] DATE_CODE_YY:0, DATE_CODE_WW:0 [2025-09-14 14:15:24.173] [2025-09-14 14:15:24.173] [SegCode] Segment Code:0x80, PROJECT_CODE:0x0, FAB_CODE:0x0, RW_STA:0x0, CTL:0x0, DCM:0x4 [2025-09-14 14:15:24.173] [2025-09-14 14:15:24.173] [PMIC]Preloader Start [2025-09-14 14:15:24.173] [2025-09-14 14:15:24.173] [PMIC]MT6357 CHIP Code = 0x5730, mrv=1 [2025-09-14 14:15:24.173] [2025-09-14 14:15:24.173] [PMIC]POWER_HOLD :0x1 [2025-09-14 14:15:24.173] [2025-09-14 14:15:24.173] [PMIC]TOP_RST_STATUS[0x152]=0x48 [2025-09-14 14:15:24.173] [2025-09-14 14:15:24.173] [PMIC]PONSTS[0xC]=0x0 [2025-09-14 14:15:24.173] [2025-09-14 14:15:24.173] [PMIC]POFFSTS[0xE]=0x400 [2025-09-14 14:15:24.173] [2025-09-14 14:15:24.173] [PMIC]PGSTATUS0[0x14]=0xFFFE [2025-09-14 14:15:24.173] [2025-09-14 14:15:24.173] [PMIC]PSOCSTATUS[0x16]=0x0 [2025-09-14 14:15:24.173] [2025-09-14 14:15:24.173] [PMIC]BUCK_OC_SDN_STATUS[0x1434]=0x0 [2025-09-14 14:15:24.173] [2025-09-14 14:15:24.173] [PMIC]BUCK_OC_SDN_EN[0x1444]=0x1E9F [2025-09-14 14:15:24.173] [2025-09-14 14:15:24.173] [PMIC]THERMALSTATUS[0x18]=0x0 [2025-09-14 14:15:24.173] [2025-09-14 14:15:24.173] [PMIC]STRUP_CON4[0xA1C]=0x0 [2025-09-14 14:15:24.173] [2025-09-14 14:15:24.173] [PMIC]TOP_RST_MISC[0x14C]=0x1204 [2025-09-14 14:15:24.173] [2025-09-14 14:15:24.173] [PMIC]TOP_CLK_TRIM[0x38E]=0x6AC0 [2025-09-14 14:15:24.173] [2025-09-14 14:15:24.173] latch VPROC 800000 uV [2025-09-14 14:15:24.204] [2025-09-14 14:15:24.204] latch VSRAM_PROC 900000 uV [2025-09-14 14:15:24.204] [2025-09-14 14:15:24.204] latch VSRAM_OTHERS 900000 uV [2025-09-14 14:15:24.204] [2025-09-14 14:15:24.204] latch VCORE 800000 uV [2025-09-14 14:15:24.204] [2025-09-14 14:15:24.204] latch VMODEM 800000 uV [2025-09-14 14:15:24.204] [2025-09-14 14:15:24.204] [pmic_check_rst] DDLO_RSTB [2025-09-14 14:15:24.204] [2025-09-14 14:15:24.204] [pmic_check_rst] AP Watchdog [2025-09-14 14:15:24.204] [2025-09-14 14:15:24.204] [PMIC]just_rst = 0 [2025-09-14 14:15:24.204] [2025-09-14 14:15:24.204] No EFUSE SW Load [2025-09-14 14:15:24.204] [2025-09-14 14:15:24.204] battery exists [2025-09-14 14:15:24.204] [2025-09-14 14:15:24.204] [PMIC]disable usbdl wo battery [2025-09-14 14:15:24.204] [2025-09-14 14:15:24.204] [PMIC]pmic_wdt_set Reg[0x14C]=0x1225 [2025-09-14 14:15:24.204] [2025-09-14 14:15:24.204] [rt5738_driver_probe] [2025-09-14 14:15:24.204] [2025-09-14 14:15:24.204] [rt5738_hw_component_detect] exist = 0, Chip ID = A801 [2025-09-14 14:15:24.204] [2025-09-14 14:15:24.204] [rt5738_driver_probe] PL rt5738_vdd2 is not exist [2025-09-14 14:15:24.204] [2025-09-14 14:15:24.204] [rt5738_hw_component_detect] exist = 0, Chip ID = A801 [2025-09-14 14:15:24.204] [2025-09-14 14:15:24.204] [rt5738_driver_probe] PL rt5738_vddq is not exist [2025-09-14 14:15:24.204] [2025-09-14 14:15:24.204] [hl7593_driver_probe] [2025-09-14 14:15:24.204] [2025-09-14 14:15:24.204] [hl7593_read_interface] Reg[3]=0xA8 [2025-09-14 14:15:24.204] [2025-09-14 14:15:24.204] [hl7593_read_interface] val=0xA8 [2025-09-14 14:15:24.204] [2025-09-14 14:15:24.204] [hl7593_read_interface] Reg[4]=0x1 [2025-09-14 14:15:24.204] [2025-09-14 14:15:24.204] [hl7593_read_interface] val=0x1 [2025-09-14 14:15:24.204] [2025-09-14 14:15:24.204] [hl7593_read_interface] Reg[5]=0x81 [2025-09-14 14:15:24.204] [2025-09-14 14:15:24.204] [hl7593_read_interface] val=0x1 [2025-09-14 14:15:24.204] [2025-09-14 14:15:24.204] PGOOD = 1, chip_id = 43009 [2025-09-14 14:15:24.204] [2025-09-14 14:15:24.204] [hl7593_hw_component_detect] exist = 1, Chip ID = A801 [2025-09-14 14:15:24.204] [2025-09-14 14:15:24.204] hl7593_vdd2_hw_init [2025-09-14 14:15:24.204] [2025-09-14 14:15:24.204] [hl7593_read_interface] Reg[0]=0xD4 [2025-09-14 14:15:24.204] [2025-09-14 14:15:24.204] [hl7593_read_interface] val=0xD4 [2025-09-14 14:15:24.204] [2025-09-14 14:15:24.204] [0x0]=0xD4 [hl7593_read_interface] Reg[1]=0xD4 [2025-09-14 14:15:24.236] [2025-09-14 14:15:24.236] [hl7593_read_interface] val=0xD4 [2025-09-14 14:15:24.236] [2025-09-14 14:15:24.236] [0x1]=0xD4 [hl7593_read_interface] Reg[2]=0x83 [2025-09-14 14:15:24.236] [2025-09-14 14:15:24.236] [hl7593_read_interface] val=0x83 [2025-09-14 14:15:24.236] [2025-09-14 14:15:24.236] [0x2]=0x83 [hl7593_read_interface] Reg[3]=0xA8 [2025-09-14 14:15:24.236] [2025-09-14 14:15:24.236] [hl7593_read_interface] val=0xA8 [2025-09-14 14:15:24.236] [2025-09-14 14:15:24.236] [0x3]=0xA8 [hl7593_read_interface] Reg[4]=0x1 [2025-09-14 14:15:24.236] [2025-09-14 14:15:24.236] [hl7593_read_interface] val=0x1 [2025-09-14 14:15:24.236] [2025-09-14 14:15:24.236] [0x4]=0x1 [hl7593_read_interface] Reg[5]=0x81 [2025-09-14 14:15:24.236] [2025-09-14 14:15:24.236] [hl7593_read_interface] val=0x81 [2025-09-14 14:15:24.236] [2025-09-14 14:15:24.236] [0x5]=0x81 [hl7593_driver_probe] PL g_hl7593_0_hw_exist=1, g_hl7593_driver_ready=1 [2025-09-14 14:15:24.236] [2025-09-14 14:15:24.236] [hl7593_read_interface] Reg[3]=0xA8 [2025-09-14 14:15:24.236] [2025-09-14 14:15:24.236] [hl7593_read_interface] val=0xA8 [2025-09-14 14:15:24.236] [2025-09-14 14:15:24.236] [hl7593_read_interface] Reg[4]=0x1 [2025-09-14 14:15:24.236] [2025-09-14 14:15:24.236] [hl7593_read_interface] val=0x1 [2025-09-14 14:15:24.236] [2025-09-14 14:15:24.236] [hl7593_read_interface] Reg[5]=0x81 [2025-09-14 14:15:24.236] [2025-09-14 14:15:24.236] [hl7593_read_interface] val=0x1 [2025-09-14 14:15:24.236] [2025-09-14 14:15:24.236] PGOOD = 1, chip_id = 43009 [2025-09-14 14:15:24.236] [2025-09-14 14:15:24.236] [hl7593_hw_component_detect] exist = 1, Chip ID = A801 [2025-09-14 14:15:24.236] [2025-09-14 14:15:24.236] hl7593_vddq_hw_init [2025-09-14 14:15:24.236] [2025-09-14 14:15:24.236] [hl7593_read_interface] Reg[0]=0x80 [2025-09-14 14:15:24.236] [2025-09-14 14:15:24.236] [hl7593_read_interface] val=0x80 [2025-09-14 14:15:24.236] [2025-09-14 14:15:24.236] [0x0]=0x80 [hl7593_read_interface] Reg[1]=0x80 [2025-09-14 14:15:24.236] [2025-09-14 14:15:24.236] [hl7593_read_interface] val=0x80 [2025-09-14 14:15:24.236] [2025-09-14 14:15:24.236] [0x1]=0x80 [hl7593_read_interface] Reg[2]=0x83 [2025-09-14 14:15:24.262] [2025-09-14 14:15:24.262] [hl7593_read_interface] val=0x83 [2025-09-14 14:15:24.262] [2025-09-14 14:15:24.262] [0x2]=0x83 [hl7593_read_interface] Reg[3]=0xA8 [2025-09-14 14:15:24.262] [2025-09-14 14:15:24.262] [hl7593_read_interface] val=0xA8 [2025-09-14 14:15:24.262] [2025-09-14 14:15:24.262] [0x3]=0xA8 [hl7593_read_interface] Reg[4]=0x1 [2025-09-14 14:15:24.262] [2025-09-14 14:15:24.262] [hl7593_read_interface] val=0x1 [2025-09-14 14:15:24.262] [2025-09-14 14:15:24.262] [0x4]=0x1 [hl7593_read_interface] Reg[5]=0x81 [2025-09-14 14:15:24.262] [2025-09-14 14:15:24.262] [hl7593_read_interface] val=0x81 [2025-09-14 14:15:24.262] [2025-09-14 14:15:24.262] [0x5]=0x81 [hl7593_driver_probe] PL g_hl7593_1_hw_exist=1, g_hl7593_driver_ready=1 [2025-09-14 14:15:24.262] [2025-09-14 14:15:24.262] [hl7593_set_voltage] id = 0, set_val = 1125000 [2025-09-14 14:15:24.262] [2025-09-14 14:15:24.262] [hl7593_read_interface] Reg[0]=0xD4 [2025-09-14 14:15:24.262] [2025-09-14 14:15:24.262] [hl7593_read_interface] val=0x54 [2025-09-14 14:15:24.262] [2025-09-14 14:15:24.262] [hl7593_get_voltage] id = 0, get_val = 1125000 [2025-09-14 14:15:24.262] [2025-09-14 14:15:24.262] hl7593_vdd2=1125000 uV [2025-09-14 14:15:24.262] [2025-09-14 14:15:24.262] [hl7593_read_interface] Reg[1]=0x80 [2025-09-14 14:15:24.262] [2025-09-14 14:15:24.262] [hl7593_read_interface] val=0x0 [2025-09-14 14:15:24.262] [2025-09-14 14:15:24.262] [hl7593_get_voltage] id = 1, get_val = 600000 [2025-09-14 14:15:24.262] [2025-09-14 14:15:24.262] hl7593_vddq=600000 uV [2025-09-14 14:15:24.262] [2025-09-14 14:15:24.262] [fan53526_driver_probe] [2025-09-14 14:15:24.262] [2025-09-14 14:15:24.262] [I2C] 365: id=3,addr: 60, transfer error [2025-09-14 14:15:24.262] [2025-09-14 14:15:24.262] [I2C] 371: I2C_ACKERR [2025-09-14 14:15:24.262] [2025-09-14 14:15:24.262] [I2C] 235: I2C structure: [2025-09-14 14:15:24.262] [2025-09-14 14:15:24.262] [I2C] Clk=24960,Id=3,Mode=1,St_rs=0,Dma_en=0,Op=3,Poll_en=1,Irq_stat=2 [2025-09-14 14:15:24.262] [2025-09-14 14:15:24.262] [I2C] Trans_len=1,Trans_num=2,Trans_auxlen=1,Data_size=FFFF,speed=100 [2025-09-14 14:15:24.297] [2025-09-14 14:15:24.297] [I2C] 238: base address 0x1100F000 [2025-09-14 14:15:24.297] [2025-09-14 14:15:24.297] [I2C] 259: I2C register: [2025-09-14 14:15:24.297] [2025-09-14 14:15:24.297] [I2C] SLAVE_ADDR=C0,INTR_MASK=1F8,INTR_STAT=3,CONTROL=38,TRANSFER_LEN=1 [2025-09-14 14:15:24.297] [2025-09-14 14:15:24.297] [I2C] TRANSAC_LEN=2,DELAY_LEN=A,TIMING=418,LTIMING=118,START=2,FIFO_STAT=1 [2025-09-14 14:15:24.297] [2025-09-14 14:15:24.297] [I2C] IO_CONFIG=1A3,HS=0,DEBUGSTAT=0,EXT_CONF=8001,TRANSFER_LEN_AUX=1,CLOCK_DIV=4 [2025-09-14 14:15:24.297] [2025-09-14 14:15:24.297] [I2C] 924: write_read 0x10001 bytes fails,ret=-121. [2025-09-14 14:15:24.297] [2025-09-14 14:15:24.297] [I2C] 365: id=3,addr: 60, transfer error [2025-09-14 14:15:24.297] [2025-09-14 14:15:24.297] [I2C] 371: I2C_ACKERR [2025-09-14 14:15:24.297] [2025-09-14 14:15:24.297] [I2C] 235: I2C structure: [2025-09-14 14:15:24.297] [2025-09-14 14:15:24.297] [I2C] Clk=24960,Id=3,Mode=1,St_rs=0,Dma_en=0,Op=3,Poll_en=1,Irq_stat=2 [2025-09-14 14:15:24.297] [2025-09-14 14:15:24.297] [I2C] Trans_len=1,Trans_num=2,Trans_auxlen=1,Data_size=FFFF,speed=100 [2025-09-14 14:15:24.297] [2025-09-14 14:15:24.297] [I2C] 238: base address 0x1100F000 [2025-09-14 14:15:24.297] [2025-09-14 14:15:24.297] [I2C] 259: I2C register: [2025-09-14 14:15:24.297] [2025-09-14 14:15:24.297] [I2C] SLAVE_ADDR=C0,INTR_MASK=1F8,INTR_STAT=3,CONTROL=38,TRANSFER_LEN=1 [2025-09-14 14:15:24.297] [2025-09-14 14:15:24.297] [I2C] TRANSAC_LEN=2,DELAY_LEN=A,TIMING=418,LTIMING=118,START=2,FIFO_STAT=1 [2025-09-14 14:15:24.297] [2025-09-14 14:15:24.297] [I2C] IO_CONFIG=1A3,HS=0,DEBUGSTAT=0,EXT_CONF=8001,TRANSFER_LEN_AUX=1,CLOCK_DIV=4 [2025-09-14 14:15:24.297] [2025-09-14 14:15:24.297] [I2C] 924: write_read 0x10001 bytes fails,ret=-121. [2025-09-14 14:15:24.297] [2025-09-14 14:15:24.297] [I2C] 365: id=3,addr: 60, transfer error [2025-09-14 14:15:24.323] [2025-09-14 14:15:24.323] [I2C] 371: I2C_ACKERR [2025-09-14 14:15:24.323] [2025-09-14 14:15:24.323] [I2C] 235: I2C structure: [2025-09-14 14:15:24.323] [2025-09-14 14:15:24.323] [I2C] Clk=24960,Id=3,Mode=1,St_rs=0,Dma_en=0,Op=3,Poll_en=1,Irq_stat=2 [2025-09-14 14:15:24.323] [2025-09-14 14:15:24.323] [I2C] Trans_len=1,Trans_num=2,Trans_auxlen=1,Data_size=FFFF,speed=100 [2025-09-14 14:15:24.323] [2025-09-14 14:15:24.323] [I2C] 238: base address 0x1100F000 [2025-09-14 14:15:24.323] [2025-09-14 14:15:24.323] [I2C] 259: I2C register: [2025-09-14 14:15:24.323] [2025-09-14 14:15:24.323] [I2C] SLAVE_ADDR=C0,INTR_MASK=1F8,INTR_STAT=3,CONTROL=38,TRANSFER_LEN=1 [2025-09-14 14:15:24.323] [2025-09-14 14:15:24.323] [I2C] TRANSAC_LEN=2,DELAY_LEN=A,TIMING=418,LTIMING=118,START=2,FIFO_STAT=1 [2025-09-14 14:15:24.323] [2025-09-14 14:15:24.323] [I2C] IO_CONFIG=1A3,HS=0,DEBUGSTAT=0,EXT_CONF=8001,TRANSFER_LEN_AUX=1,CLOCK_DIV=4 [2025-09-14 14:15:24.323] [2025-09-14 14:15:24.323] [I2C] 924: write_read 0x10001 bytes fails,ret=-121. [2025-09-14 14:15:24.323] [2025-09-14 14:15:24.323] [fan53526_hw_component_detect] exist = 0, Chip ID = 304 [2025-09-14 14:15:24.323] [2025-09-14 14:15:24.323] [fan53526_driver_probe] PL fan53526_vdd2 is not exist [2025-09-14 14:15:24.323] [2025-09-14 14:15:24.323] [fan53526_hw_component_detect] exist = 0, Chip ID = A801 [2025-09-14 14:15:24.323] [2025-09-14 14:15:24.323] [fan53526_driver_probe] PL fan53526_vddq is not exist [2025-09-14 14:15:24.323] [2025-09-14 14:15:24.323] register vs1 OK [2025-09-14 14:15:24.323] [2025-09-14 14:15:24.323] register vmodem OK [2025-09-14 14:15:24.323] [2025-09-14 14:15:24.323] register vcore OK [2025-09-14 14:15:24.323] [2025-09-14 14:15:24.323] register vproc OK [2025-09-14 14:15:24.323] [2025-09-14 14:15:24.323] register vpa OK [2025-09-14 14:15:24.323] [2025-09-14 14:15:24.323] register vsram_others OK [2025-09-14 14:15:24.323] [2025-09-14 14:15:24.323] register vsram_proc OK [2025-09-14 14:15:24.323] [2025-09-14 14:15:24.323] register vdram OK [2025-09-14 14:15:24.323] [2025-09-14 14:15:24.323] [PMIC]Init done [2025-09-14 14:15:24.323] [2025-09-14 14:15:24.323] [SD0] Host controller intialization start [2025-09-14 14:15:24.336] [2025-09-14 14:15:24.336] [SD0] SET_CLK(260kHz): SCLK(259kHz) MODE(0) DDR(0) DIV(385) DS(0) RS(0) [2025-09-14 14:15:24.336] [2025-09-14 14:15:24.336] [SD0] Host controller intialization done [2025-09-14 14:15:24.336] [2025-09-14 14:15:24.336] [mmc_init]: msdc0 start mmc_init_card() [2025-09-14 14:15:24.336] [2025-09-14 14:15:24.336] [mmc_init_card]: start [2025-09-14 14:15:24.336] [2025-09-14 14:15:24.391] [SD0] EXT_CSD_ERASE_GRP_DEF is Off, wp_size = 8192KB [2025-09-14 14:15:24.391] [2025-09-14 14:15:24.391] [SD0] csd.write_prot_grpsz = 15, csd.erase_sctsz = 1024 [2025-09-14 14:15:24.391] [2025-09-14 14:15:24.391] [SD0] Switch to High-Speed mode! [2025-09-14 14:15:24.391] [2025-09-14 14:15:24.391] [SD0] Switch to DDR buswidth [2025-09-14 14:15:24.391] [2025-09-14 14:15:24.391] [SD0] SET_CLK(260kHz): SCLK(259kHz) MODE(2) DDR(1) DIV(192) DS(0) RS(0) [2025-09-14 14:15:24.391] [2025-09-14 14:15:24.391] [SD0] Size: 7296 MB, Max.Speed: 52000 kHz, blklen(512), nblks(14942208) [2025-09-14 14:15:24.391] [2025-09-14 14:15:24.391] [SD0] Initialized, eMMC45 [2025-09-14 14:15:24.391] [2025-09-14 14:15:24.391] [SD0] SET_CLK(52000kHz): SCLK(50000kHz) MODE(2) DDR(1) DIV(1) DS(0) RS(0) [2025-09-14 14:15:24.391] [2025-09-14 14:15:24.391] [mmc_init_card]: finish successfully [2025-09-14 14:15:24.391] [2025-09-14 14:15:24.391] [PLFM] Init Boot Device: OK(0) [2025-09-14 14:15:24.391] [2025-09-14 14:15:24.391] [PLFM] Init PWRAP: OK(0) [2025-09-14 14:15:24.391] [2025-09-14 14:15:24.391] [PLFM] Init PMIC: OK(0) [2025-09-14 14:15:24.391] [2025-09-14 14:15:24.391] [PLFM] chip_hw_ver[CA01], chip_sw_ver[1] [2025-09-14 14:15:24.391] [2025-09-14 14:15:24.391] [2025-09-14 14:15:24.391] [2025-09-14 14:15:24.391] [BLDR] Build Time: 20230323-154644 [2025-09-14 14:15:24.391] [2025-09-14 14:15:24.391] clk_buf_dump_dts_log: PMIC_CLK_BUF?_STATUS=2 1 1 2 0 0 0 [2025-09-14 14:15:24.391] [2025-09-14 14:15:24.391] clk_buf_dump_dts_log: PMIC_CLK_BUF?_DRV_CURR=1 1 1 1 1 1 1 [2025-09-14 14:15:24.391] [2025-09-14 14:15:24.391] clk_buf_dump_clkbuf_log DCXO_CW00/02/11/13/14/15/16/20/top_spi_con1=0x4E1D 3AEE 8000 98E9 82B5 A2AA 9455 11 1 [2025-09-14 14:15:24.391] [2025-09-14 14:15:24.391] clk_buf_dump_clkbuf_log DCXO_CW00/02/11/13/14/15/16/20/top_spi_con1=0x4E1D 3AEE 8000 98E9 82B5 A2AA 9455 11 0 [2025-09-14 14:15:24.391] [2025-09-14 14:15:24.391] clk_buf_init_pmic_wrap: DCXO_CONN_ADR0/WDATA0/ADR1/WDATA1=0x44A/0/44A/1 [2025-09-14 14:15:24.419] [2025-09-14 14:15:24.419] clk_buf_init_pmic_wrap: DCXO_NFC_ADR0/WDATA0/ADR1/WDATA1/EN=0x78C/100/78A/100/3 [2025-09-14 14:15:24.419] [2025-09-14 14:15:24.419] [RTC]enable_dcxo first con = 0x486, osc32con = 0xDE72, sec = 0x2544 [2025-09-14 14:15:24.419] [2025-09-14 14:15:24.419] [RTC]get_frequency_meter: input=0x0, ouput=5 [2025-09-14 14:15:24.419] [2025-09-14 14:15:24.419] [RTC]get_frequency_meter: input=0x0, ouput=0 [2025-09-14 14:15:24.419] [2025-09-14 14:15:24.420] [RTC]get_frequency_meter: input=0x0, ouput=0 [2025-09-14 14:15:24.420] [2025-09-14 14:15:24.420] [RTC]get_frequency_meter: input=0x0, ouput=5 [2025-09-14 14:15:24.420] [2025-09-14 14:15:24.420] [RTC]get_frequency_meter: input=0x0, ouput=3935 [2025-09-14 14:15:24.420] [2025-09-14 14:15:24.420] [RTC]rtc_init#1 powerkey1 = 0xA357, powerkey2 = 0x67D2, without LPD [2025-09-14 14:15:24.420] [2025-09-14 14:15:24.420] [RTC]bbpu = 0x1, con = 0x486, osc32con = 0xDE72, sec = 0x2544, yea = 0xC102 [2025-09-14 14:15:24.420] [2025-09-14 14:15:24.420] [RTC]rtc_init#2 powerkey1 = 0xA357, powerkey2 = 0x67D2 [2025-09-14 14:15:24.420] [2025-09-14 14:15:24.420] [RTC]rtc_init Writeif_unlock [2025-09-14 14:15:24.420] [2025-09-14 14:15:24.420] [RTC]switch to dcxo [2025-09-14 14:15:24.420] [2025-09-14 14:15:24.420] [RTC]eosc_cali: RG_FQMTR_CKSEL=0x42 [2025-09-14 14:15:24.420] [2025-09-14 14:15:24.420] [RTC]get_frequency_meter: input=0xF, ouput=724 [2025-09-14 14:15:24.420] [2025-09-14 14:15:24.420] [RTC]eosc_cali: val=0x2D4 [2025-09-14 14:15:24.420] [2025-09-14 14:15:24.420] [RTC]get_frequency_meter: input=0x17, ouput=892 [2025-09-14 14:15:24.420] [2025-09-14 14:15:24.420] [RTC]eosc_cali: val=0x37C [2025-09-14 14:15:24.420] [2025-09-14 14:15:24.420] [RTC]get_frequency_meter: input=0x13, ouput=808 [2025-09-14 14:15:24.420] [2025-09-14 14:15:24.420] [RTC]eosc_cali: val=0x328 [2025-09-14 14:15:24.420] [2025-09-14 14:15:24.420] [RTC]get_frequency_meter: input=0x11, ouput=766 [2025-09-14 14:15:24.447] [2025-09-14 14:15:24.447] [RTC]eosc_cali: val=0x2FE [2025-09-14 14:15:24.447] [2025-09-14 14:15:24.447] [RTC]get_frequency_meter: input=0x12, ouput=787 [2025-09-14 14:15:24.447] [2025-09-14 14:15:24.447] [RTC]eosc_cali: val=0x313 [2025-09-14 14:15:24.447] [2025-09-14 14:15:24.447] [RTC]get_frequency_meter: input=0x12, ouput=787 [2025-09-14 14:15:24.447] [2025-09-14 14:15:24.447] [RTC]get_frequency_meter: input=0x13, ouput=808 [2025-09-14 14:15:24.447] [2025-09-14 14:15:24.447] [RTC]EOSC cali val = 0xDE52 [2025-09-14 14:15:24.447] [2025-09-14 14:15:24.447] [RTC]RTC_SPAR0=0x0 [2025-09-14 14:15:24.447] [2025-09-14 14:15:24.447] [RTC]XO_XMODE_M = 1 , XO_EN32K_M = 1 [2025-09-14 14:15:24.447] [2025-09-14 14:15:24.447] [RTC]32k-less mode [2025-09-14 14:15:24.447] [2025-09-14 14:15:24.447] [RTC]rtc_2sec_reboot_check 0x2544, without 2sec reboot, type 0x2 [2025-09-14 14:15:24.447] [2025-09-14 14:15:24.447] [RTC]rtc_2sec_stat_clear [2025-09-14 14:15:24.447] [2025-09-14 14:15:24.447] [RTC]rtc_lpd_init RTC_CON=0x486 [2025-09-14 14:15:24.447] [2025-09-14 14:15:24.447] [PMIC] pmic_init_setting end. v180413 [2025-09-14 14:15:24.447] [2025-09-14 14:15:24.447] [MT6357] 1 6,61 [2025-09-14 14:15:24.447] [2025-09-14 14:15:24.447] [MT6357] 1 2,45 [2025-09-14 14:15:24.447] [2025-09-14 14:15:24.447] [MT6357] 1 1,48 [2025-09-14 14:15:24.447] [2025-09-14 14:15:24.447] [MT6357] get volt 5, 61, 900000 [2025-09-14 14:15:24.447] [2025-09-14 14:15:24.447] vsram_others = 900000 uV [2025-09-14 14:15:24.447] [2025-09-14 14:15:24.447] [MT6357] get volt 3, 45, 800000 [2025-09-14 14:15:24.447] [2025-09-14 14:15:24.447] vproc = 800000 uV [2025-09-14 14:15:24.447] [2025-09-14 14:15:24.447] [MT6357] get volt 6, 61, 900000 [2025-09-14 14:15:24.447] [2025-09-14 14:15:24.447] vsram_proc = 900000 uV [2025-09-14 14:15:24.447] [2025-09-14 14:15:24.447] [MT6357] get volt 2, 45, 800000 [2025-09-14 14:15:24.447] [2025-09-14 14:15:24.447] vcore = 800000 uV [2025-09-14 14:15:24.447] [2025-09-14 14:15:24.447] [MT6357] get volt 1, 48, 800000 [2025-09-14 14:15:24.447] [2025-09-14 14:15:24.447] vmodem = 800000 uV [2025-09-14 14:15:24.447] [2025-09-14 14:15:24.447] [MT6357] 2 6,1 [2025-09-14 14:15:24.447] [2025-09-14 14:15:24.447] [MT6357] 2 5,1 [2025-09-14 14:15:24.447] [2025-09-14 14:15:24.447] [MT6357] 2 3,1 [2025-09-14 14:15:24.447] [2025-09-14 14:15:24.447] [MT6357] 2 2,1 [2025-09-14 14:15:24.447] [2025-09-14 14:15:24.447] [MT6357] 2 1,1 [2025-09-14 14:15:24.447] [2025-09-14 14:15:24.447] [RGU] EMI_DCS_SUCCESS 0 [2025-09-14 14:15:24.447] [2025-09-14 14:15:24.447] [RGU] DVFSRC_SUCCESS 0 [2025-09-14 14:15:24.477] [2025-09-14 14:15:24.477] [DDR Reserve] ddr reserve mode not be enabled yet [2025-09-14 14:15:24.477] [2025-09-14 14:15:24.477] [RGU] mtk_wdt_mode_config mode value=30, tmp:22000030 [2025-09-14 14:15:24.477] [2025-09-14 14:15:24.477] [RGU] mtk_wdt_mode_config mode value=7D, tmp:2200007D [2025-09-14 14:15:24.477] [2025-09-14 14:15:24.477] [RGU] g_rgu_status: 2 (0x2) [2025-09-14 14:15:24.477] [2025-09-14 14:15:24.477] [RGU] bypass pwrkey: set [2025-09-14 14:15:24.477] [2025-09-14 14:15:24.477] Enter mtk_kpd_gpio_set! [2025-09-14 14:15:24.477] [2025-09-14 14:15:24.477] after set KP enable: KP_SEL = 0x1C70 ! [2025-09-14 14:15:24.477] [2025-09-14 14:15:24.477] [RTC]irqsta = 0x0, pdn1 = 0x0, pdn2 = 0x201, spar0 = 0x80, spar1 = 0x800 [2025-09-14 14:15:24.477] [2025-09-14 14:15:24.477] [RTC]new_spare0 = 0xE000, new_spare1 = 0x5001, new_spare2 = 0x1, new_spare3 = 0x1 [2025-09-14 14:15:24.477] [2025-09-14 14:15:24.477] [RTC]bbpu = 0x1, con = 0x486, cali = 0x2544, osc32con = 0xDE72 [2025-09-14 14:15:24.477] [2025-09-14 14:15:24.477] pmic_reboot: 0! [2025-09-14 14:15:24.477] [2025-09-14 14:15:24.477] [PLFM] WDT reboot bypass power key! [2025-09-14 14:15:24.477] [2025-09-14 14:15:24.477] [PMIC]POWER_HOLD :0x1 [2025-09-14 14:15:24.477] [2025-09-14 14:15:24.477] [RTC]rtc_lpsd_solution [2025-09-14 14:15:24.477] [2025-09-14 14:15:24.477] [RTC]1st RTC_AL_MASK= 0x7F [2025-09-14 14:15:24.477] [2025-09-14 14:15:24.477] [RTC]2nd RTC_AL_MASK= 0x7F [2025-09-14 14:15:24.477] [2025-09-14 14:15:24.477] [RTC]rtc_bbpu_power_on done [2025-09-14 14:15:24.477] [2025-09-14 14:15:24.477] pl chr:1 monitor:1 plchr:1 gain:1042 [2025-09-14 14:15:24.477] [2025-09-14 14:15:24.477] mtk_kpd_gpio_set Already! [2025-09-14 14:15:24.477] [2025-09-14 14:15:24.477] key 1 is pressed [2025-09-14 14:15:24.477] [2025-09-14 14:15:24.477] Vol Up detected. Log Keep on. [2025-09-14 14:15:24.477] [2025-09-14 14:15:24.477] [dramc] init partition address is 0x0000000000008000 [2025-09-14 14:15:24.477] [2025-09-14 14:15:24.477] [dramc] init SRAM region for DRAM exception detection [2025-09-14 14:15:24.477] [2025-09-14 14:15:24.477] [dramc] LAST_DRAM_FATAL_ERR_FLAG = 0x0 [2025-09-14 14:15:24.509] [2025-09-14 14:15:24.509] for cold boot, always return 0 [2025-09-14 14:15:24.509] [2025-09-14 14:15:24.509] [RGU] rgu_update_reg: 0, bits: 0x400, addr: 0x10007040, val: 0x200F1 [2025-09-14 14:15:24.509] [2025-09-14 14:15:24.509] [RGU] WDT DDR reserve mode FAIL! 200F1 [2025-09-14 14:15:24.509] [2025-09-14 14:15:24.509] [RGU] DDR RESERVE Success 0 [2025-09-14 14:15:24.509] [2025-09-14 14:15:24.509] [RGU] rgu_update_reg: 0, bits: 0x200, addr: 0x10007040, val: 0x200F1 [2025-09-14 14:15:24.509] [2025-09-14 14:15:24.509] [RGU] rgu_update_reg: 0, bits: 0x100, addr: 0x10007040, val: 0x200F1 [2025-09-14 14:15:24.509] [2025-09-14 14:15:24.509] [MT6357] 4 2,1 [2025-09-14 14:15:24.509] [2025-09-14 14:15:24.509] [MT6357] 2 7,0 [2025-09-14 14:15:24.509] [2025-09-14 14:15:24.509] [hl7593_enable] id =0, en =1, ret =1 [2025-09-14 14:15:24.509] [2025-09-14 14:15:24.509] [hl7593_enable] id =1, en =1, ret =1 [2025-09-14 14:15:24.509] [2025-09-14 14:15:24.509] [hl7593_set_voltage] id = 1, set_val = 600000 [2025-09-14 14:15:24.509] [2025-09-14 14:15:24.509] [hl7593_set_voltage] id = 0, set_val = 1125000 [2025-09-14 14:15:24.509] [2025-09-14 14:15:24.509] [MT6357] 1 2,45 [2025-09-14 14:15:24.509] [2025-09-14 14:15:24.509] [MT6357] get volt 2, 45, 800000 [2025-09-14 14:15:24.509] [2025-09-14 14:15:24.509] Vcore = 800000 [2025-09-14 14:15:24.509] [2025-09-14 14:15:24.509] [hl7593_read_interface] Reg[0]=0xD4 [2025-09-14 14:15:24.509] [2025-09-14 14:15:24.509] [hl7593_read_interface] val=0x54 [2025-09-14 14:15:24.509] [2025-09-14 14:15:24.509] [hl7593_get_voltage] id = 0, get_val = 1125000 [2025-09-14 14:15:24.509] [2025-09-14 14:15:24.509] Vdram = 1125000 [2025-09-14 14:15:24.509] [2025-09-14 14:15:24.509] [hl7593_read_interface] Reg[1]=0x80 [2025-09-14 14:15:24.509] [2025-09-14 14:15:24.509] [hl7593_read_interface] val=0x0 [2025-09-14 14:15:24.509] [2025-09-14 14:15:24.509] [hl7593_get_voltage] id = 1, get_val = 600000 [2025-09-14 14:15:24.509] [2025-09-14 14:15:24.509] Vddq = 600000 [2025-09-14 14:15:24.509] [2025-09-14 14:15:24.509] [EMI] mcp_dram_num:2,discrete_dram_num:0,enable_combo_dis:0 [2025-09-14 14:15:24.509] [2025-09-14 14:15:24.509] eMMC cid: F401224D,51353131,47114F21,D332C03 [2025-09-14 14:15:24.529] [2025-09-14 14:15:24.529] found:0,i:2 [2025-09-14 14:15:24.529] [2025-09-14 14:15:24.529] [EMI] MDL number = -1 [2025-09-14 14:15:24.529] [2025-09-14 14:15:24.529] [EMI] setting failed 0xFFFFFFFF [2025-09-14 14:15:24.529] [2025-09-14 14:15:24.529] <ASSERT> /home/xc-buildsrv/jks-t-alps-release-r0.mp1-V5/vendor/mediatek/proprietary/bootable/bootloader/preloader/platform/mt6761/src/drivers/emi.c:line 1730 0 [2025-09-14 14:15:24.529] 解析一下这段日志
09-15
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