NS3编译时忽略warnings

摘自https://www.nsnam.org/wiki/HOWTO_build_old_versions_of_ns-3_on_newer_compilers


To disable warnings from breaking your build, do the following:

 CXXFLAGS="-Wall" ./waf configure
 ./waf -vv
`timescale 1ns / 1ps module tb_frequency_meter_top(); // 输入信号 reg clk_50M; // 50MHz系统时钟 reg signal_in; // 被测信号输入 reg reset_n; // 异步复位(低有效) reg range_sel; // 量程选择(0:低频 1:高频) // 输出信号 wire [6:0] seg; // 七段数码管段选 wire [5:0] sel; // 数码管位选 wire [1:0] unit; // 单位指示(00:Hz, 01:kHz, 10:MHz) // 测试端口 wire clk_10Hz_test; wire clk_1MHz_test; wire [23:0] freq_count_test; wire [23:0] period_count_test; wire [23:0] display_value_test; // 实例化被测设计 frequency_meter_top uut ( .clk_50M(clk_50M), .signal_in(signal_in), .reset_n(reset_n), .range_sel(range_sel), .seg(seg), .sel(sel), .unit(unit), // 测试端口 .clk_10Hz_test(clk_10Hz_test), .clk_1MHz_test(clk_1MHz_test), .freq_count_test(freq_count_test), .period_count_test(period_count_test), .display_value_test(display_value_test) ); // 生成50MHz系统时钟 always #10 clk_50M = ~clk_50M; // 20ns周期 = 50MHz // 测试序列 initial begin // 初始化信号 clk_50M = 0; signal_in = 0; reset_n = 0; range_sel = 0; // 复位系统 #100; reset_n = 1; #100; $display("Starting simulation at time %0t ns", $time); // 测试1:低频信号测量 (1kHz) $display("\n=== Test 1: Low frequency measurement (1kHz) ==="); range_sel = 0; // 选择低频量程 generate_signal(1000, 10); // 1kHz,持续10ms #10_000_000; // 等待10ms (10,000,000 ns) // 测试2:高频信号测量 (1MHz) $display("\n=== Test 2: High frequency measurement (1MHz) ==="); range_sel = 1; // 选择高频量程 generate_signal(1_000_000, 1); // 1MHz,持续1ms #1_000_000; // 等待1ms (1,000,000 ns) // 测试3:边界频率测量 (100Hz) $display("\n=== Test 3: Boundary frequency (100Hz) ==="); range_sel = 0; // 选择低频量程 generate_signal(100, 100); // 100Hz,持续100ms #100_000_000; // 等待100ms // 极高频测量 (10MHz) $display("\n=== Test 4: High frequency boundary (10MHz) ==="); range_sel = 1; // 选择高频量程 generate_signal(10_000_000, 0.1); // 10MHz,持续0.1ms #100_000; // 等待0.1ms (100,000 ns) // 量程切换测试 $display("\n=== Test 5: Range switching test ==="); // 低频量程 range_sel = 0; generate_signal(500, 10); // 500Hz,持续10ms #10_000_000; // 等待10ms // 高频量程 range_sel = 1; generate_signal(500, 10); // 500Hz,持续10ms #10_000_000; // 等待10ms // 结束仿真 #100; $display("\nSimulation completed at time %0t ns", $time); $finish; end // 修改后的信号生成任务(使用整数替代实数) task generate_signal; input integer freq; // 频率值 (Hz) - 整数 input integer duration; // 持续时间 (ms) - 整数 integer half_period; // 半周期时间 (ns) - 整数 integer total_time_ns; // 总时间 (ns) - 整数 integer start_time; // 开始时间 - 整数 integer cycles; // 信号周期数 integer i; // 循环计数器 begin $display("Generating signal: %d Hz for %d ms", freq, duration); // 防止除零错误 if (freq <= 0) begin $display("Error: Frequency must be positive!"); half_period = 1000; // 默认1us半周期 end else begin // 计算半周期时间(纳秒) - 使用整数除法 half_period = 500_000_000 / freq; // 1e9/2 = 500,000,000 end // 计算总时间(纳秒) - 使用整数 total_time_ns = duration * 1_000_000; // 计算完整周期数 cycles = (total_time_ns) / (2 * half_period); $display("Half period: %d ns, Cycles: %d", half_period, cycles); // 使用循环生成信号 for (i = 0; i < cycles; i = i + 1) begin signal_in = 1; #(half_period); signal_in = 0; #(half_period); end // 信号结束后保持低电平 signal_in = 0; end endtask // 数码管显示监控 initial begin reg [23:0] digit_str [0:5]; // 存储每个数码管的字符串表示 integer i; // 循环变量声明在外部 forever begin #100_000; // 每100us检查一次显示 (0.1ms) if (reset_n) begin $display("\n===== Display at time %0t ns =====", $time); $display("Digit select: %b", sel); $display("Segment pattern: %b", seg); // 解码所有数码管 - 使用外部声明的循环变量 for (i = 0; i < 6; i = i + 1) begin decode_digit(seg, sel[i], digit_str[i]); end $display("Decoded digits: %s %s %s %s %s %s", digit_str[0], digit_str[1], digit_str[2], digit_str[3], digit_str[4], digit_str[5]); // 显示单位 case (unit) 2&#39;b00: $display("Unit: Hz"); 2&#39;b01: $display("Unit: kHz"); 2&#39;b10: $display("Unit: MHz"); default: $display("Unit: Unknown"); endcase $display("==================="); end end end // 数码管解码任务 task decode_digit; input [6:0] segs; input sel_bit; output reg [23:0] digit_str; // 字符串输出 begin if (!sel_bit) begin digit_str = "OFF"; end else begin case (segs) 7&#39;b1000000: digit_str = "0 "; 7&#39;b1111001: digit_str = "1 "; 7&#39;b0100100: digit_str = "2 "; 7&#39;b0110000: digit_str = "3 "; 7&#39;b0011001: digit_str = "4 "; 7&#39;b0010010: digit_str = "5 "; 7&#39;b0000010: digit_str = "6 "; 7&#39;b1111000: digit_str = "7 "; 7&#39;b0000000: digit_str = "8 "; 7&#39;b0010000: digit_str = "9 "; 7&#39;b0001000: digit_str = "A "; 7&#39;b0000011: digit_str = "B "; 7&#39;b1000110: digit_str = "C "; 7&#39;b0100001: digit_str = "D "; 7&#39;b0000110: digit_str = "E "; 7&#39;b0001110: digit_str = "F "; default: digit_str = "? "; endcase end end endtask // 内部信号监控 initial begin forever begin #1_000_000; // 每1ms检查一次内部信号 if (reset_n) begin $display("\n--- Internal signals at time %0t ns ---", $time); $display("clk_10Hz: %b", clk_10Hz_test); $display("clk_1MHz: %b", clk_1MHz_test); $display("freq_count: %d", freq_count_test); $display("period_count: %d", period_count_test); $display("display_value: %d", display_value_test); $display("-----------------------"); end end end endmodule Error (10174): Verilog HDL Unsupported Feature error at tb_frequency_meter_top.v(56): system function "$time" is not supported for synthesis Error (10174): Verilog HDL Unsupported Feature error at tb_frequency_meter_top.v(97): system function "$time" is not supported for synthesis Error (12153): Can&#39;t elaborate top-level user hierarchy Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 3 errors, 6 warnings Error: Peak virtual memory: 4609 megabytes Error: Processing ended: Mon Jun 16 10:09:15 2025 Error: Elapsed time: 00:00:01 Error: Total CPU time (on all processors): 00:00:00 Error (293001): Quartus II Full Compilation was unsuccessful. 5 errors, 6 warnings 运行时出现这些问题怎么解决
06-17
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