<?xml version="1.0" encoding="utf-8" ?><rss version="2.0"><channel><title><![CDATA[LovingDuo的博客]]></title><description><![CDATA[]]></description><link>https://blog.youkuaiyun.com/LovingDuo</link><language>zh-cn</language><generator>https://blog.youkuaiyun.com/</generator><copyright><![CDATA[Copyright &copy; LovingDuo]]></copyright><item><title><![CDATA[脉冲同步器]]></title><link>https://blog.youkuaiyun.com/LovingDuo/article/details/77723219</link><guid>https://blog.youkuaiyun.com/LovingDuo/article/details/77723219</guid><author>LovingDuo</author><pubDate>Wed, 30 Aug 2017 20:42:40 +0800</pubDate><description><![CDATA[verilog实现上面的电路：


module pulse_syc(
    input sclk_1,
    input sclk_2,
    input p_in,
    output p_out,
    output p_out1
);
    reg p_in_reg=0;
    reg delay0,delay1,delay2;
    wire mu]]></description><category></category></item><item><title><![CDATA[XILINX rom ram IP 核 如何编写coe 文件]]></title><link>https://blog.youkuaiyun.com/LovingDuo/article/details/74992745</link><guid>https://blog.youkuaiyun.com/LovingDuo/article/details/74992745</guid><author>LovingDuo</author><pubDate>Tue, 11 Jul 2017 19:05:00 +0800</pubDate><description><![CDATA[这张截图来自xilinx  RAM IP核使用文档：
修改数字为2   10   16  分别表示输入的数据为二进制，十进制 ，16进制  。
数据隔开可以是空格或者是逗号，最后一个数据后面加分号]]></description><category></category></item><item><title><![CDATA[verilog parameter localparam  define使用]]></title><link>https://blog.youkuaiyun.com/LovingDuo/article/details/74990036</link><guid>https://blog.youkuaiyun.com/LovingDuo/article/details/74990036</guid><author>LovingDuo</author><pubDate>Tue, 11 Jul 2017 17:37:00 +0800</pubDate><description><![CDATA[define，是宏定义，全局有效。则在整个工程都是有效

parameter，参数，可以由调用者修改参数值。在定义模块和例化的时候有一定的差别，在定义模块时：模块名在参数的前面；例化模块时：参数在实例化名的前面
简单举例：
定义模块

module clkgen
#(
 parameter COUNT=4'd15
)
(
 input clk,
 
 output  cl]]></description><category></category></item><item><title><![CDATA[序列检测]]></title><link>https://blog.youkuaiyun.com/LovingDuo/article/details/68941618</link><guid>https://blog.youkuaiyun.com/LovingDuo/article/details/68941618</guid><author>LovingDuo</author><pubDate>Sat, 01 Apr 2017 10:14:29 +0800</pubDate><description><![CDATA[module sequence_detect
(
 input clk,
 input rst_n,
 
 input din_en,
 input din,
 
 output dout


);


//capture the posedge of din_en for data receive
reg din_en_r0,din_en_r1;


alwa]]></description><category></category></item><item><title><![CDATA[Verilog  程序输出0 1 2 3 3 2 1 0 0 1 2 3 3 2 1 0.....]]></title><link>https://blog.youkuaiyun.com/LovingDuo/article/details/68941273</link><guid>https://blog.youkuaiyun.com/LovingDuo/article/details/68941273</guid><author>LovingDuo</author><pubDate>Sat, 01 Apr 2017 09:47:20 +0800</pubDate><description><![CDATA[module shixisheng(
    input clk,
    output [2:0] data,
    input rst
    );
    
    reg isNeg;  //1 increase  ;0 downto
    reg [2:0]rData;
    always@(posedge clk or negedge rst)
        ]]></description><category></category></item><item><title><![CDATA[奇数分频]]></title><link>https://blog.youkuaiyun.com/LovingDuo/article/details/65631731</link><guid>https://blog.youkuaiyun.com/LovingDuo/article/details/65631731</guid><author>LovingDuo</author><pubDate>Fri, 24 Mar 2017 15:56:36 +0800</pubDate><description><![CDATA[实现一个上升沿触发的占空比不为50%的n分频信号
在实现一个下降沿触发的占空比不为50%的n分频信号
将两路信号相与

module clkn(clr,clk,clkout);
input clr;
input clk;
output clkout;


reg rise_clkn;
reg down_clkn;
reg [3:0] rCount;
reg [3:0] d]]></description><category></category></item><item><title><![CDATA[VIVADO FIR IP使用方法]]></title><link>https://blog.youkuaiyun.com/LovingDuo/article/details/53736831</link><guid>https://blog.youkuaiyun.com/LovingDuo/article/details/53736831</guid><author>LovingDuo</author><pubDate>Mon, 19 Dec 2016 11:31:27 +0800</pubDate><description><![CDATA[在matlab中使用fdatool设计自己想要的数字滤波器，然后保存文件为.coe文件。
在vivado中调用FIR IP核，在Select Source处，选择COE File。
在Filter Type中可以选择插值，抽取等选项。

Number of Channels 和Number of Paths 分别设置通道数为3和路径数为2（通道之间是时分多路复用，相当于一个帧有3个时隙；路]]></description><category></category></item><item><title><![CDATA[解决ISE14.7在win10中不稳定的问题]]></title><link>https://blog.youkuaiyun.com/LovingDuo/article/details/53736594</link><guid>https://blog.youkuaiyun.com/LovingDuo/article/details/53736594</guid><author>LovingDuo</author><pubDate>Mon, 19 Dec 2016 11:09:29 +0800</pubDate><description><![CDATA[https://www.xilinx.com/support/answers/62380.html
这个网址是xilinx官网的解决这个问题的连接


解决的方法：
将“ISE\lib\nt64\libPortability.dll”和"ISE\lib\nt64\libPortabilityNOSH.dll"文件备份


第二步：将libPortability.dll”重命名为“l]]></description><category></category></item><item><title><![CDATA[verilog PWM实现呼吸灯]]></title><link>https://blog.youkuaiyun.com/LovingDuo/article/details/53213135</link><guid>https://blog.youkuaiyun.com/LovingDuo/article/details/53213135</guid><author>LovingDuo</author><pubDate>Fri, 18 Nov 2016 10:24:10 +0800</pubDate><description><![CDATA[使用PWM技术实现呼吸灯。利用占空比每1ms递增1us的占空比来点亮LED。没隔1s实现灯由逐渐变亮到逐渐变暗，或者逐渐变暗到逐渐变量的转换。使用的语言是verilog。

module led_breath
//#(
// parameter    LED_WIDTH = 4
//)
(
 input    clk,  //global clock
 input    rst_n]]></description><category></category></item><item><title><![CDATA[Vivado DDS IP使用的时候波形不是正弦波]]></title><link>https://blog.youkuaiyun.com/LovingDuo/article/details/53202113</link><guid>https://blog.youkuaiyun.com/LovingDuo/article/details/53202113</guid><author>LovingDuo</author><pubDate>Thu, 17 Nov 2016 16:39:15 +0800</pubDate><description><![CDATA[使用vivado提供的DDS  IP核时，我使用的是SIN COS LUT only模式。正确的提供相位的输入。默认的情况下显示的不是波形
我们需要右击我们想观察的信号，然后选择Waveform Style==>analog。就可以观察波形了。如果不修改Radix，得到的波形是这样的



   要想观察到正余弦信号，需要将Radix 修改为 signed Decimal]]></description><category></category></item><item><title><![CDATA[ise工程移植到vivado中]]></title><link>https://blog.youkuaiyun.com/LovingDuo/article/details/52789772</link><guid>https://blog.youkuaiyun.com/LovingDuo/article/details/52789772</guid><author>LovingDuo</author><pubDate>Tue, 11 Oct 2016 17:18:16 +0800</pubDate><description><![CDATA[通过这四步可以将ise中的工程导入到vivado中。如果ise工程中使用的IP核在vivado中已经升级了，也就是说ise中的IP核版本太低。如果我们任然要使用ISE中的IP核，我们可以把该IP核的网表文件，添加到我们想使用的工程中。]]></description><category></category></item><item><title><![CDATA[Linux 下安装vivado2014.4]]></title><link>https://blog.youkuaiyun.com/LovingDuo/article/details/52396871</link><guid>https://blog.youkuaiyun.com/LovingDuo/article/details/52396871</guid><author>LovingDuo</author><pubDate>Thu, 01 Sep 2016 10:24:49 +0800</pubDate><description><![CDATA[1.在里xilinx的官网下载vivado的linux版本的安装包,我下载的是2014.4版本的，tar.gz格式的
2.直接使用指令    tar  xvzf   文件名.tar.gz
3进入你解压缩之后的文件夹  然后执行 sudo ./xsetup]]></description><category></category></item><item><title><![CDATA[Ubuntu 安装sogou输入法]]></title><link>https://blog.youkuaiyun.com/LovingDuo/article/details/52389315</link><guid>https://blog.youkuaiyun.com/LovingDuo/article/details/52389315</guid><author>LovingDuo</author><pubDate>Wed, 31 Aug 2016 21:53:09 +0800</pubDate><description><![CDATA[1.首先进入搜狗输入法的官网去下载输入法的linux版本
2.sudo apt-get install gdebi 安装这一个工具
3.cd   下载的某狗文件所在目录

4.sudo gdebi   安装包的全名
5.重新启动一遍]]></description><category></category></item><item><title><![CDATA[linux firefox能正常那个上网，但是在软件中心却不能下载软件]]></title><link>https://blog.youkuaiyun.com/LovingDuo/article/details/52388364</link><guid>https://blog.youkuaiyun.com/LovingDuo/article/details/52388364</guid><author>LovingDuo</author><pubDate>Wed, 31 Aug 2016 20:14:19 +0800</pubDate><description><![CDATA[failed to download repository information
ying gai shi nide linux banfen tai di.
shenji nide xitong 

shiyong 

sudo apt-get upgrate;]]></description><category></category></item><item><title><![CDATA[VHDL inout与buffer]]></title><link>https://blog.youkuaiyun.com/LovingDuo/article/details/52330918</link><guid>https://blog.youkuaiyun.com/LovingDuo/article/details/52330918</guid><author>LovingDuo</author><pubDate>Fri, 26 Aug 2016 18:36:23 +0800</pubDate><description><![CDATA[VHDL中BUFFER与INOUT有什么区别呢?首先INOUT完全是双向的，也就是
INOUT：=IN+OUT,对INOUT属性的PIN既可以写出也可以读入，他有2个寄存器，如
...
port(a:inout std_logic);
...
signal ccc,ddd:bit
process(clk)
begin
...
a
...
ddd
BUFFER： 一般比较少用]]></description><category></category></item><item><title><![CDATA[好的流水灯程序 Verilog]]></title><link>https://blog.youkuaiyun.com/LovingDuo/article/details/52303070</link><guid>https://blog.youkuaiyun.com/LovingDuo/article/details/52303070</guid><author>LovingDuo</author><pubDate>Wed, 24 Aug 2016 18:37:52 +0800</pubDate><description><![CDATA[module stream(
    input clk,
    input reset,
    output [7:0] led
    );
    reg [31:0]count;
    reg [7:0]led;


    parameter[31:0] delay=32'd100000000; //delay 1 sec
always@(posedge clk]]></description><category></category></item><item><title><![CDATA[VHDL 测试文件模板]]></title><link>https://blog.youkuaiyun.com/LovingDuo/article/details/52269185</link><guid>https://blog.youkuaiyun.com/LovingDuo/article/details/52269185</guid><author>LovingDuo</author><pubDate>Sun, 21 Aug 2016 20:20:24 +0800</pubDate><description><![CDATA[entity testbench is


end testbench;


architecture Behavioral of testbench is
component fredevider3 is
port(
    clock:in std_logic;
    clkout:out std_logic
);
end component fredevider3;]]></description><category></category></item><item><title><![CDATA[流水灯2]]></title><link>https://blog.youkuaiyun.com/LovingDuo/article/details/52205525</link><guid>https://blog.youkuaiyun.com/LovingDuo/article/details/52205525</guid><author>LovingDuo</author><pubDate>Sun, 14 Aug 2016 18:09:17 +0800</pubDate><description><![CDATA[工具：vivado2015.2  板子：ZedBoard
module stream(
    input clk,
    input reset,
    output [7:0] led
    );
    reg [31:0]count;
    reg [3:0] num;
    reg [7:0]led;


    parameter[31:0] delay]]></description><category></category></item><item><title><![CDATA[ZedBoard流水灯]]></title><link>https://blog.youkuaiyun.com/LovingDuo/article/details/52205278</link><guid>https://blog.youkuaiyun.com/LovingDuo/article/details/52205278</guid><author>LovingDuo</author><pubDate>Sun, 14 Aug 2016 17:26:45 +0800</pubDate><description><![CDATA[使用的工具Vivado2015.2   
代码如下：

module light(
   input clk,
    input reset,
    output [7:0]led
    );
    reg[31:0]count;
    reg [7:0]led;
    reg [2:0]num;
    parameter [31:0]delay=32'd100]]></description><category></category></item><item><title><![CDATA[解决ISE使用过程中出现 _SN.exe的问题]]></title><link>https://blog.youkuaiyun.com/LovingDuo/article/details/51943088</link><guid>https://blog.youkuaiyun.com/LovingDuo/article/details/51943088</guid><author>LovingDuo</author><pubDate>Mon, 18 Jul 2016 16:26:16 +0800</pubDate><description><![CDATA[鼠标左单击击ISE桌面的快捷方式，将目标地址从G:\ise14\14.7\ISE_DS\settings64.bat G:\ise14\14.7\ISE_DS\ISE\bin\nt64\ise.exe。
修改为
G:\ise14\14.7\ISE_DS\settings32.bat G:\ise14\14.7\ISE_DS\ISE\bin\nt\ise.exe]]></description><category></category></item></channel></rss>