<?xml version="1.0" encoding="utf-8" ?><rss version="2.0"><channel><title><![CDATA[Lou245的博客]]></title><description><![CDATA[]]></description><link>https://blog.youkuaiyun.com/Lou245</link><language>zh-cn</language><generator>https://blog.youkuaiyun.com/</generator><copyright><![CDATA[Copyright &copy; Lou245]]></copyright><item><title><![CDATA[system verilog foreach]]></title><link>https://blog.youkuaiyun.com/Lou245/article/details/162190788</link><guid>https://blog.youkuaiyun.com/Lou245/article/details/162190788</guid><author>Lou245</author><pubDate>Mon, 22 Jun 2026 09:52:09 +0800</pubDate><description><![CDATA[1.foreach 里边的continue，代表只是终止本次foreach分支，后面foreach分支会继续执行。2.foreach里边的break，代表终止本次及其后面所有的foreach分支。]]></description><category></category></item><item><title><![CDATA[system verilog多行代码宏]]></title><link>https://blog.youkuaiyun.com/Lou245/article/details/162105705</link><guid>https://blog.youkuaiyun.com/Lou245/article/details/162105705</guid><author>Lou245</author><pubDate>Thu, 18 Jun 2026 17:48:37 +0800</pubDate><description><![CDATA[2. 最后一行不能加\。1. 每行后用\结束。3. \后不能加空格。]]></description><category></category></item><item><title><![CDATA[MCU的firmware总结]]></title><link>https://blog.youkuaiyun.com/Lou245/article/details/161884063</link><guid>https://blog.youkuaiyun.com/Lou245/article/details/161884063</guid><author>Lou245</author><pubDate>Tue, 16 Jun 2026 17:14:39 +0800</pubDate><description><![CDATA[从 SRAM 启动（调试用）2） 配置字 / 选项字节（Option Bytes），有些 MCU 用 Flash 里的特殊配置字决定启动地址，比引脚更灵活。3） 硬件地址映射，部分 MCU 会把不同存储区域映射到同一个地址，由硬件自动选择。即固件，直接控制硬件的底层代码，和硬件绑定非常紧密，一般存在 Flash/ROM 里。从boot启动，但是运行可以跳转至sram rom flash的地址。1) 启动引脚（Boot Pins），MCU 有专用的。会被映射到 Flash 或 ROM，取决于启动配置。]]></description><category></category></item><item><title><![CDATA[(二十二) system verilog类学习笔记]]></title><link>https://blog.youkuaiyun.com/Lou245/article/details/147561360</link><guid>https://blog.youkuaiyun.com/Lou245/article/details/147561360</guid><author>Lou245</author><pubDate>Sun, 27 Apr 2025 15:17:19 +0800</pubDate><description><![CDATA[子类方法中使用super，可以实现子类句柄访问父类的方法。子类无需任何操作，即可访问父类的变量。父类句柄无论如何都不能访问子类的对象。⑤父类句柄不能访问子类对象。]]></description><category></category></item><item><title><![CDATA[(二十一) UVM_TLM通信学习笔记]]></title><link>https://blog.youkuaiyun.com/Lou245/article/details/147489345</link><guid>https://blog.youkuaiyun.com/Lou245/article/details/147489345</guid><author>Lou245</author><pubDate>Thu, 24 Apr 2025 18:14:54 +0800</pubDate><description><![CDATA[②在B component中声明export import端口，build phase例化，声明put/get/transport等task/function，connect phase中连接export  import。①在A component中声明port端口，build phase例化，main phase调用import所在组件声明的put/get/transport等task/function。④如果是阻塞，B component中可以声明task/function；]]></description><category></category></item><item><title><![CDATA[(十九) UVM_seq学习笔记]]></title><link>https://blog.youkuaiyun.com/Lou245/article/details/147398522</link><guid>https://blog.youkuaiyun.com/Lou245/article/details/147398522</guid><author>Lou245</author><pubDate>Mon, 21 Apr 2025 17:18:57 +0800</pubDate><description><![CDATA[grap比lock优先级更高，lock是被插入sqr仲裁队列的最后面，等到它时，前面的仲裁请求已经结束，grap则被放入sqr仲裁队列的最前面。如果一个seq已经lock，另一seq执行grap，会等之前的lock执行完，再执行grap。default_seq的raise和drop，替换为，sqr中main phse会启动seq基类的starting phase，在seq中使用starting phase进行raise和drop。①同一个sqr启动多个seq，存在sqr仲裁问题。]]></description><category></category></item><item><title><![CDATA[(二十) Config_db学习笔记]]></title><link>https://blog.youkuaiyun.com/Lou245/article/details/147395320</link><guid>https://blog.youkuaiyun.com/Lou245/article/details/147395320</guid><author>Lou245</author><pubDate>Mon, 21 Apr 2025 15:20:40 +0800</pubDate><description><![CDATA[]]></description><category></category></item><item><title><![CDATA[(十八) AMBA-AHB学习笔记]]></title><link>https://blog.youkuaiyun.com/Lou245/article/details/147386657</link><guid>https://blog.youkuaiyun.com/Lou245/article/details/147386657</guid><author>Lou245</author><pubDate>Mon, 21 Apr 2025 11:54:26 +0800</pubDate><description><![CDATA[]]></description><category></category></item><item><title><![CDATA[(十七) System verilog练习]]></title><link>https://blog.youkuaiyun.com/Lou245/article/details/147249086</link><guid>https://blog.youkuaiyun.com/Lou245/article/details/147249086</guid><author>Lou245</author><pubDate>Tue, 15 Apr 2025 14:13:24 +0800</pubDate><description><![CDATA[如果想编译完立即运行，不用单独执行./simv这一步，可以用-R命令。编译：vcs –full64 –sverilog module.sv。]]></description><category></category></item><item><title><![CDATA[(十四) 验证边界场景]]></title><link>https://blog.youkuaiyun.com/Lou245/article/details/147228064</link><guid>https://blog.youkuaiyun.com/Lou245/article/details/147228064</guid><author>Lou245</author><pubDate>Mon, 14 Apr 2025 17:02:44 +0800</pubDate><description><![CDATA[]]></description><category></category></item><item><title><![CDATA[(十一) System Verilog module]]></title><link>https://blog.youkuaiyun.com/Lou245/article/details/147142279</link><guid>https://blog.youkuaiyun.com/Lou245/article/details/147142279</guid><author>Lou245</author><pubDate>Fri, 11 Apr 2025 13:49:20 +0800</pubDate><description><![CDATA[]]></description><category></category></item><item><title><![CDATA[(十) Interface使用注意事项]]></title><link>https://blog.youkuaiyun.com/Lou245/article/details/147139595</link><guid>https://blog.youkuaiyun.com/Lou245/article/details/147139595</guid><author>Lou245</author><pubDate>Fri, 11 Apr 2025 11:18:06 +0800</pubDate><description><![CDATA[]]></description><category></category></item></channel></rss>