网卡手册阅读：ixgbe 发包流程研究

最新推荐文章于 2023-12-16 10:14:31 发布

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最新推荐文章于 2023-12-16 10:14:31 发布

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分类专栏：数据手册阅读文章标签： ixgbe 发包流程 tx ring

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本文介绍了一种基于寄存器的传输描述符管理机制，包括传输描述符基地址寄存器(TDBA)、长度寄存器(TDLEN)及头尾寄存器(TDH/TDT)，阐述了它们如何共同协作实现高效的数据传输过程。描述了寄存器在主机内存中的作用，特别是TDH和TDT如何指示正在进行和已完成的数据传输，并讨论了软件如何检测硬件处理状态。

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Transmit Descriptor Base Address register (TDBA 0-127) — This register indicates the start address of the descriptor ring buffer in the host memory; this 64-bit address is aligned on a 16-byte boundary and is stored in two consecutive 32-bit registers. Hardware ignores the lower four bits.

传输描述符基地址寄存器，这个寄存器存储主机内存中描述符 ring buffer 的起始地址，这个 64 位地址以 16-byte 为单位对齐，使用两个 32 位的寄存器存储。

Transmit Descriptor Length register (TDLEN 0-127) — This register determines the
number of bytes allocated to the circular buffer. This value must be 0 modulo 128.

传输描述符长度寄存器，这个寄存器确定环形缓冲区中申请的字节数目。

TDH 寄存器中保存相对起始地址的偏移量，指向当前正在被硬件处理的描述符。传输队列由 head 与 tail 之间的描述符指针组成。

Transmit Descriptor Head register (TDH 0-127) — This register holds a value that is an offset from the base and indicates the in-progress descriptor. There can be up to 64 K minus 8 descriptors in the circular buffer. The transmit queue consists of the descriptors between the head and tail pointers. Transmission starts with the descriptor pointer by the head registers. When the DMA engine processes a descriptor, it might optionally write back the completed descriptor and then advance the head pointer. It then processes the next descriptor up to the point that the head pointer reaches the tail. Head equals tail means that the transmit queue in host memory is empty. Reading this register indicates the hardware progress to the software. All descriptors behind the head pointer and in front of tail register are owned by the software. The other descriptors are owned by the hardware and should not be modified by the software.

传输从 TDH 寄存器指向的描述符指针开始。当 DMA 引擎处理了一个描述符，它将会选择性回写已经完成的描述符并拨动 head 指针。DMA 引擎然后处理下一个描述符直到 head 指针与 tail 指针指向位置重叠。head 与 tail 指向相同位置意味着主机内存中的传输队列为空。

读取 TDH 寄存器表明硬件正在处理软件投递的报文。所有在 TDH 之后与 TDT 之前的描述符属于软件所有，其它的描述符属于硬件所有，软件不应该修改它。

这里指针向下拨动表示向前，向上拨动表示向后。0-127 是向前，127 - 0 是向后。

软硬件划分的不同区域见下图：
在这里插入图片描述

Transmit Descriptor Tail register (TDT 0-127) — This register holds a value, which is an offset from the base, and indicates the location beyond the last descriptor hardware can process. Software adds new descriptors to the ring by writing descriptors in the circular buffer pointed by the tail pointer. The new descriptor(s) are indicated to hardware by updating the tail pointer one descriptor above the last added descriptor. Note that a single packet or TSO might be composed of multiple descriptors. The transmit tail pointer should never point to the middle of a packet or TSO, which might cause undesired software/hardware races.

TDT 寄存器中保存一个值，这个值是相对基地址的偏移量，这个值表明了最后一个硬件能够处理的描述符的位置。软件通过写入新的描述符到 tail 指针指向的环形缓冲区来添加新的描述符到 ring 中。通知硬件有新的描述符添加的过程是通过将 tail 指针更新到上一个添加的描述符之后的下一个位置完成的。需要注意的是单个包、TSO 可能由多个描述符组成。TDT 指针应当永远不会指向一个 packet 或 TSO 中间，这种情况将会导致预想不到的的软件、硬件竞争情况。

Software might detect which packets have already been processed by hardware using the following:

• Read the TDH head register to determine which packets (those logically before the head) have been transferred to the on-chip FIFO or transmitted. This method is not recommended as races between the internal update of the head register and the actual write back of descriptors can occur.

• When head write back is enabled (TDWBAL[n].Head_WB_En = 1b) software might read the image of the head pointer in host memory at the address defined by TDWBAH[n]/TDWBAL[n] pair. Hardware updates the head image in host memory by completed descriptors as described in Section 7.2.3.5.2.

• When head write back is not enabled (TDWBAL[n].Head_WB_En = 0b), software might track the DD bits in the descriptor ring. Descriptor write back is controlled by the RS bit and the WTHRESH setting as well as interrupt assertion.

• Issue an interrupt. An interrupt condition is generated each time a packet was transmitted or received and a descriptor was write back or transmit queue goes empty (EICR.RTxQ[0-19]). This interrupt can either be enabled or masked. All of the registers controlling the descriptor rings behavior should be set before transmit is enabled.

软件通过如下方式检测一个包是否已经被硬件处理：

读取 TDH 寄存器，确定哪个包已经被传输到了芯片中的 FIFO 或已经传输完成。不建议使用这种方法，在这种方法中内部更新 head 寄存器的过程与实际描述符回写过程可能出现竞争。
当 head 回写被使能（TDWBAL[n].Head_WB_En 位置 1）软件可以读取主机内存中在 TDWBAH[n]/TDWBAL[n] 对中存储的 head 指针指向的内容。硬件将会在完成描述符传输后更新主机内存中 head pointer 指向的内容。
当 head 回写没有使能，软件可以跟踪描述符 ring 中的 DD 位。描述符回写将由 RS 位与 WTHRESH 设置，也可以使用中断来控制
触发一个中断。每次当一个包被传输完成或接收完成、描述符被回写、传输队列为空都将会触发一个中断条件。这些中断被使能、屏蔽。在传输被使能之前所有控制描述符 ring 的寄存器行为都必须被设定。