<?xml version="1.0" encoding="utf-8" ?><rss version="2.0"><channel><title><![CDATA[Jazel的博客]]></title><description><![CDATA[]]></description><link>https://blog.youkuaiyun.com/Jazel</link><language>zh-cn</language><generator>https://blog.youkuaiyun.com/</generator><copyright><![CDATA[Copyright &copy; Jazel]]></copyright><item><title><![CDATA[DDR5 Write leveling详解]]></title><link>https://blog.youkuaiyun.com/Jazel/article/details/155561047</link><guid>https://blog.youkuaiyun.com/Jazel/article/details/155561047</guid><author>Jazel</author><pubDate>Fri, 05 Dec 2025 10:42:24 +0800</pubDate><description><![CDATA[DDR5 上电Calibration中至关重要的一环：write leveling]]></description><category></category></item><item><title><![CDATA[DDR5 1N/2N 模式]]></title><link>https://blog.youkuaiyun.com/Jazel/article/details/155014287</link><guid>https://blog.youkuaiyun.com/Jazel/article/details/155014287</guid><author>Jazel</author><pubDate>Wed, 19 Nov 2025 10:10:10 +0800</pubDate><description><![CDATA[DDR5基础知识：1N/2N 模式]]></description><category></category></item><item><title><![CDATA[FreeRTOS与ARM，FPGA上的部署]]></title><link>https://blog.youkuaiyun.com/Jazel/article/details/128896508</link><guid>https://blog.youkuaiyun.com/Jazel/article/details/128896508</guid><author>Jazel</author><pubDate>Wed, 08 Feb 2023 15:39:17 +0800</pubDate><description><![CDATA[FreeRTOS与ARM，FPGA上的部署，概念以及联系]]></description><category></category></item><item><title><![CDATA[IMXRT1050开发板使用问题记录]]></title><link>https://blog.youkuaiyun.com/Jazel/article/details/128214658</link><guid>https://blog.youkuaiyun.com/Jazel/article/details/128214658</guid><author>Jazel</author><pubDate>Wed, 08 Feb 2023 10:59:50 +0800</pubDate><description><![CDATA[IMXRT1050开发板使用问题记录]]></description><category></category></item><item><title><![CDATA[TI ADS1299使用BUG记录]]></title><link>https://blog.youkuaiyun.com/Jazel/article/details/127720122</link><guid>https://blog.youkuaiyun.com/Jazel/article/details/127720122</guid><author>Jazel</author><pubDate>Sun, 06 Nov 2022 20:04:18 +0800</pubDate><description><![CDATA[基于Kintex-7系列FPGA驱动ADS1299开发过程中的BUG记录]]></description><category></category></item><item><title><![CDATA[米联客udp_stack以太网协议栈使用教程]]></title><link>https://blog.youkuaiyun.com/Jazel/article/details/127180008</link><guid>https://blog.youkuaiyun.com/Jazel/article/details/127180008</guid><author>Jazel</author><pubDate>Thu, 06 Oct 2022 11:08:31 +0800</pubDate><description><![CDATA[使用米联客udp_stack.dcp开发以太网的教程]]></description><category></category></item><item><title><![CDATA[Lattice Propel开发SoC项目BUG集 ＞＞持续更新ing]]></title><link>https://blog.youkuaiyun.com/Jazel/article/details/127137245</link><guid>https://blog.youkuaiyun.com/Jazel/article/details/127137245</guid><author>Jazel</author><pubDate>Sat, 01 Oct 2022 20:39:41 +0800</pubDate><description><![CDATA[记录博主在Lattice Shanghai实习期间使用Lattice Propel SDK和Lattice Propel Builder开发Lattice SoC工程中遇到的Bug及其解决方式。
（此问题极易诱发脑血栓10级，如果解决了你的问题，一定要点赞）]]></description><category></category></item><item><title><![CDATA[米联客含协议栈.dcp的工程仿真]]></title><link>https://blog.youkuaiyun.com/Jazel/article/details/126802140</link><guid>https://blog.youkuaiyun.com/Jazel/article/details/126802140</guid><author>Jazel</author><pubDate>Sun, 11 Sep 2022 09:42:08 +0800</pubDate><description><![CDATA[使用新买的米联客K7开发板跑以太网通信的时候，使用的是米联客自己写的.dcp协议栈，然后仿真中是不能够直接调用的，本博客记录了解决方案。]]></description><category></category></item><item><title><![CDATA[2023秋招英特尔Intel 软件/FPGA真题回忆录]]></title><link>https://blog.youkuaiyun.com/Jazel/article/details/126778226</link><guid>https://blog.youkuaiyun.com/Jazel/article/details/126778226</guid><author>Jazel</author><pubDate>Fri, 09 Sep 2022 11:10:38 +0800</pubDate><description><![CDATA[2023秋招英特尔Intel 软件/FPGA真题回忆录]]></description><category></category></item><item><title><![CDATA[研究生电子设计大赛参赛心得]]></title><link>https://blog.youkuaiyun.com/Jazel/article/details/126463771</link><guid>https://blog.youkuaiyun.com/Jazel/article/details/126463771</guid><author>Jazel</author><pubDate>Mon, 22 Aug 2022 14:01:34 +0800</pubDate><description><![CDATA[研究生电子设计大赛参赛心得]]></description><category></category></item><item><title><![CDATA[Lattice Propel在线Debug/Run]]></title><link>https://blog.youkuaiyun.com/Jazel/article/details/126373504</link><guid>https://blog.youkuaiyun.com/Jazel/article/details/126373504</guid><author>Jazel</author><pubDate>Tue, 16 Aug 2022 20:26:05 +0800</pubDate><description><![CDATA[本文介绍的是Propel SDK中 Run和debug的使用，在使用了一段时间Propel(Propel SDK & Propel builder)这个“新手劝退软件 ”后，认为十分有必要记录一下部分操作以帮助新手绕过大坑！]]></description><category></category></item><item><title><![CDATA[Lattice Radiant烧写程序]]></title><link>https://blog.youkuaiyun.com/Jazel/article/details/126235374</link><guid>https://blog.youkuaiyun.com/Jazel/article/details/126235374</guid><author>Jazel</author><pubDate>Mon, 08 Aug 2022 20:34:23 +0800</pubDate><description><![CDATA[Lattice Radiant烧写程序教程]]></description><category></category></item><item><title><![CDATA[使用Xilinx Vivado重新设置IP参数时出错]]></title><link>https://blog.youkuaiyun.com/Jazel/article/details/126189488</link><guid>https://blog.youkuaiyun.com/Jazel/article/details/126189488</guid><author>Jazel</author><pubDate>Sat, 06 Aug 2022 09:34:00 +0800</pubDate><description><![CDATA[Vivado报错提示Generate of output products did not run again as all output products were previously generated and up-to-date.]]></description><category></category></item><item><title><![CDATA[Lattice Diamond设置Notepad++为默认编辑器]]></title><link>https://blog.youkuaiyun.com/Jazel/article/details/126022184</link><guid>https://blog.youkuaiyun.com/Jazel/article/details/126022184</guid><author>Jazel</author><pubDate>Wed, 27 Jul 2022 20:03:55 +0800</pubDate><description><![CDATA[Lattice Diamond设置Notepad++为默认编辑器]]></description><category></category></item><item><title><![CDATA[lattice的Diamond或Radiant打不开Modelsim]]></title><link>https://blog.youkuaiyun.com/Jazel/article/details/126014330</link><guid>https://blog.youkuaiyun.com/Jazel/article/details/126014330</guid><author>Jazel</author><pubDate>Wed, 27 Jul 2022 14:49:55 +0800</pubDate><description><![CDATA[Lattice的Diamond或者Radiant打不开Modelsim]]></description><category></category></item><item><title><![CDATA[震惊~Signal ＜XXX＞ missing in the sensitivity list is added for synthesis purposes在verilog中警告的解决方法]]></title><link>https://blog.youkuaiyun.com/Jazel/article/details/108881823</link><guid>https://blog.youkuaiyun.com/Jazel/article/details/108881823</guid><author>Jazel</author><pubDate>Wed, 30 Sep 2020 11:01:36 +0800</pubDate><description><![CDATA[你是否还在为秃头而烦恼？
你是否还在通宵为了赶项目而焦急？
朋友，你不是 一个人!
看看吧，下面是这个bug的描述：
WARNING:HDLCompiler:91 - "F:\FPGA_Doc\AD_test\uart.v" Line 56: Signal &lt;symbol&gt; missing in the sensitivity list is added for synthesis purposes. HDL and post-synthesis simulations may differ a]]></description><category></category></item><item><title><![CDATA[震惊！！！Linux上安装Github报错：Permission denied (publickey)问题]]></title><link>https://blog.youkuaiyun.com/Jazel/article/details/108255768</link><guid>https://blog.youkuaiyun.com/Jazel/article/details/108255768</guid><author>Jazel</author><pubDate>Thu, 27 Aug 2020 11:17:55 +0800</pubDate><description><![CDATA[震惊！！！Linux上安装Github报错：Permission denied (publickey)问题
1.报错内容：No more authentication methods to try. git@github.com: Permission denied (publickey).

2.进程：楼主已经完成了本地添加ssh秘钥以及在github上添加ssh秘钥；
然而绝望的楼主在不断尝试将SSH公钥添加到github后依然验证失败之后（如上图所示），终于找到了最终解：
3.首先输入
ssh-age]]></description><category></category></item><item><title><![CDATA[震惊·X话最少的~“原理图更新到PCB时出现Unknown Pin： PinXXX 问题解决方案”]]></title><link>https://blog.youkuaiyun.com/Jazel/article/details/107340019</link><guid>https://blog.youkuaiyun.com/Jazel/article/details/107340019</guid><author>Jazel</author><pubDate>Tue, 14 Jul 2020 16:15:58 +0800</pubDate><description><![CDATA[使用Altium Designer时，被它强大功能折服的你，是否有遇到过下面这令你绝望的问题呢？
废话不多说，直接上干货：

检查 “报错元器件” 的Scheme引脚与PCB封装的引脚是否有不对应的地方（如D3-3就是元件D3的第三个引脚）


如果从这里看到的Pin Designerator与PCB引脚不对应的话，当然就要直接改啦！
改完后，想要局部更新到PCBDoc，可以点击PCBDoc界面的Update XXX，也可以点击 原理图上的Design-&gt; Update PCB document XX]]></description><category></category></item><item><title><![CDATA[ISE报错NgdBuild:604解决方法]]></title><link>https://blog.youkuaiyun.com/Jazel/article/details/106992266</link><guid>https://blog.youkuaiyun.com/Jazel/article/details/106992266</guid><author>Jazel</author><pubDate>Sun, 28 Jun 2020 09:26:28 +0800</pubDate><description><![CDATA[@ISE报错NgdBuild:604解决方法
在使用ISE编写FPGA代码时，从其他地方导入 .v文件，运行时会报图片中的错误。
解决方法：在单纯的复制黏贴.v文件并且导入到 ISE 的同时，把 .ngc文件拷贝过来，如下图所示：


Rerun后即可解决问题
初次上传博文哈，有不对的地方欢迎各位大佬指教



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