`uvm_analysis_imp_decl（）宏的使用

詹姆撕邦德

已于 2023-10-28 21:33:44 修改

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CC 4.0 BY-SA版权

文章标签：硬件工程

于 2023-10-28 21:31:23 首次发布

本文链接：https://blog.youkuaiyun.com/JamesBond619/article/details/134095087

本文讨论了在UVM(UniversalVerificationMethodology)中，当分析组件需要处理多路数据而写入接口仅有一个时，如何使用uvm_analysis_imp_decl解决。重点介绍了my_scoreboard类中write函数的定义，以及my_env环境类的connect_phase中数据连接的过程。

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1. 主要解决问题：当出现analysis_imp所在的component需要接收多路数据的情况时，但write只有一个，那么该如何定义write函数呢？这时就用到了宏uvm_analysis_imp_decl。

1）函数的定义

`uvm_analysis_imp_decl(_monitor)
`uvm_analysis_imp_decl(_model)
class my_scoreboard extends uvm_scoreboard;
		my_transaction tr;
		
		uvm_analysis_imp_monitor#(my_transaction ,my_scoreboard) monitor_imp;
		uvm_analysis_imp_model#(my_transaction ,my_scoreboard) model_imp;
		
		extern function void write_monitor(my_transaction tr);
		extern function void write_model(my_transaction tr);
        extern function void build_phase(uvm_phase phase);
endclass
function void my_scoreboard::write_monitor(my_transaction tr);

endfunction
function void my_scoreboard::write_model(my_transaction tr);

endfunction

function my_scoreboard::void build_phase(uvm_phase phase);
    super.build_phase(phase);
    monitor_imp = new("monitor_imp", this);
    model_imp   = new("model_imp", this);
endfunction: build_phase

2. 在env的connect phase 连接：


class my_env extends uvm_env;
		my_monitor my_mon;
		my_model my_mdl;
        my_scoreboard my_scb;
	
		extern function void build_phase(uvm_phase phase);
        extern function void connect_phase(uvm_phase phase);
endclass
function void  my_env::build_phase (uvm_phase phase);
    my_mon =  my_monitor::type_id::create("my_mon", this);
    my_mdl =  my_model::type_id::create("my_mdl", this);
    my_scb =  my_scoreboard ::type_id::create("my_scb", this);
endfunction

function void my_env::connect_phase(uvm_phase phase);
		super.connect_phase(phase);
		my_mon.connect(my_scb.monitor_imp);
		my_mdl.connect(my_scb.model_imp);
endfunction

3. 在my_monitor和my_model中的使用

class my_monitor extends uvm_component;
        `uvm_component_utils(my_monitor);
        uvm_analysis_port#(my_transaction) A_ap;//定义端口类型
        extern function void build_phase();
        extern task void main_phase();
endclass
function void my_monitor::build_phase(uvm_phase phase);
        super.build_phase(phase);
        A_ap = new("A_port",this);//例化端口
endfunction
task my_monitor::main_phase(uvm_phase phase);
        my_transaction tr;
        tr = new("tr");
        assert(tr.randomize());
        A_ap.write(tr);//发送tr数据包
endtask

class my_modle extends uvm_component;
        `uvm_component_utils(my_monitor );
        uvm_analysis_port#(my_transaction) A_ap;//定义端口类型
        extern function void build_phase();
        extern task void main_phase();
endclass
function void my_monitor::build_phase(uvm_phase phase);
        super.build_phase(phase);
        A_ap = new("A_port",this);//例化端口
endfunction
task my_monitor::main_phase(uvm_phase phase);
        my_transaction tr;
        tr = new("tr");
        assert(tr.randomize());
        A_ap.write(tr);//发送tr数据包
endtask