【verilog】杭电-数电实验5 多路数据选择器设计实验

源代码

`timescale 1ns / 1ps

module JK2 (
    C1,
    J1,
    K1,
    S1,
    R1,
    Q1,
    Q1_,
    C2,
    J2,
    K2,
    S2,
    R2,
    Q2,
    Q2_
);
  input C1, J1, K1, S1, R1, C2, J2, K2, S2, R2;
  output Q1, Q1_, Q2, Q2_;
  JK uut1 (
      C1,
      J1,
      K1,
      S1,
      R1,
      Q1,
      Q1_
  );
  JK uut2 (
      C2,
      J2,
      K2,
      S2,
      R2,
      Q2,
      Q2_
  );
endmodule

`timescale 1ns / 1ps

module JK (
    input clk,
    input J,
    input K,
    input set,
    input reset,
    output reg q,
    output q_
);
  always @(negedge clk, negedge set, negedge reset) begin
    if (~set && ~reset) q <= 1'bz;
    else if (~set) q <= 1'b1;
    else if (~reset) q <= 1'b0;
    else
      case ({
        J, K
      })
        2'b00:   q <= q;
        2'b01:   q <= 1'b0;
        2'b10:   q <= 1'b1;
        2'b11:   q <= ~q;
        default: q <= 1'bx;
      endcase
  end
  assign q_ = ~q;
endmodule

引脚

set_property IOSTANDARD LVCMOS18 [get_ports Q1_]
set_property IOSTANDARD LVCMOS18 [get_ports Q2]
set_property IOSTANDARD LVCMOS18 [get_ports Q2_]
set_property IOSTANDARD LVCMOS18 [get_ports R1]
set_property IOSTANDARD LVCMOS18 [get_ports R2]
set_property IOSTANDARD LVCMOS18 [get_ports S1]
set_property IOSTANDARD LVCMOS18 [get_ports S2]
set_property PULLTYPE PULLDOWN [get_ports C2]
set_property PULLTYPE PULLDOWN [get_ports J1]
set_property PULLTYPE PULLDOWN [get_ports K1]
set_property PULLTYPE PULLDOWN [get_ports K2]
set_property PULLTYPE PULLDOWN [get_ports J2]
set_property PULLTYPE PULLDOWN [get_ports Q1]
set_property PULLTYPE PULLDOWN [get_ports Q1_]
set_property PULLTYPE PULLDOWN [get_ports Q2]
set_property PULLTYPE PULLDOWN [get_ports Q2_]
set_property PULLTYPE PULLDOWN [get_ports R1]
set_property PULLTYPE PULLDOWN [get_ports R2]
set_property PULLTYPE PULLDOWN [get_ports S1]
set_property PULLTYPE PULLDOWN [get_ports S2]
set_property PACKAGE_PIN P2 [get_ports Q1]
set_property PACKAGE_PIN P1 [get_ports Q1_]
set_property PACKAGE_PIN N2 [get_ports Q2]
set_property PACKAGE_PIN M1 [get_ports Q2_]
set_property PACKAGE_PIN R4 [get_ports C1]
set_property PACKAGE_PIN AA4 [get_ports C2]
set_property PACKAGE_PIN T3 [get_ports S1]
set_property PACKAGE_PIN U3 [get_ports R1]
set_property PACKAGE_PIN T4 [get_ports J1]
set_property PACKAGE_PIN V3 [get_ports K1]
set_property PACKAGE_PIN V4 [get_ports S2]
set_property PACKAGE_PIN W4 [get_ports R2]
set_property PACKAGE_PIN Y4 [get_ports J2]
set_property PACKAGE_PIN Y6 [get_ports K2]
set_property IOSTANDARD LVCMOS18 [get_ports C1]
set_property IOSTANDARD LVCMOS18 [get_ports C2]
set_property IOSTANDARD LVCMOS18 [get_ports J1]
set_property IOSTANDARD LVCMOS18 [get_ports J2]
set_property IOSTANDARD LVCMOS18 [get_ports K1]
set_property IOSTANDARD LVCMOS18 [get_ports K2]
set_property IOSTANDARD LVCMOS18 [get_ports Q1]
set_property PULLTYPE PULLDOWN [get_ports C1]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets C1]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets S1]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets R1]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets C2]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets S2]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets R2]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]

仿真

`timescale 1ns / 1ps

module sim;
  reg C1, J1, K1, S1, R1, C2, J2, K2, S2, R2;
  wire Q1, Q1_, Q2, Q2_;
  JK2 uut (
      C1,
      J1,
      K1,
      S1,
      R1,
      Q1,
      Q1_,
      C2,
      J2,
      K2,
      S2,
      R2,
      Q2,
      Q2_
  );
  initial begin
    C1 <= 0;
    J1 <= 1;
    K1 <= 0;
    S1 <= 1;
    R1 <= 1;
    C2 <= 0;
    J2 <= 0;
    K2 <= 1;
    S2 <= 1;
    R2 <= 1;
    #10 R1 = 0;
    #10 R1 = 1;
  end
  always begin
    #100{J1, K1} <= 2'b11;
    {J2, K2} <= 2'b10;
    #100{J1, K1} <= 2'b00;
    {J2, K2} <= 2'b11;
    #100{J1, K1} <= 2'b01;
    {J2, K2} <= 2'b00;
  end
  always begin
    #17 C1 <= ~C1;
    C2 <= ~C2;

  end
endmodule