【verilog】杭电-数电实验3 译码器设计实验

源代码

`timescale 1ns / 1ps

module Decoder (
    A,
    E1,
    E2_low,
    E3_low,
    Y_low
);
  input [2:0] A;
  input E1;
  input E2_low;
  input E3_low;
  output [7:0] Y_low;
  reg [7:0] Y_low;
  always @(A or E1 or E2_low or E3_low) begin
    if (E1 && ~E2_low && ~E3_low)
      case (A)
        3'b000:  Y_low = 8'b11111110;
        3'b001:  Y_low = 8'b11111101;
        3'b010:  Y_low = 8'b11111011;
        3'b011:  Y_low = 8'b11110111;
        3'b100:  Y_low = 8'b11101111;
        3'b101:  Y_low = 8'b11011111;
        3'b110:  Y_low = 8'b10111111;
        3'b111:  Y_low = 8'b01111111;
        default: Y_low = 8'b11111111;
      endcase
    else Y_low = 8'b11111111;
  end
endmodule

引脚

set_property IOSTANDARD LVCMOS18 [get_ports {A[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {A[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {A[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {Y_low[7]}]
set_property IOSTANDARD LVCMOS18 [get_ports {Y_low[6]}]
set_property IOSTANDARD LVCMOS18 [get_ports {Y_low[5]}]
set_property IOSTANDARD LVCMOS18 [get_ports {Y_low[4]}]
set_property IOSTANDARD LVCMOS18 [get_ports {Y_low[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports {Y_low[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {Y_low[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {Y_low[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports E1]
set_property IOSTANDARD LVCMOS18 [get_ports E2_low]
set_property IOSTANDARD LVCMOS18 [get_ports E3_low]
set_property PULLTYPE PULLDOWN [get_ports {A[2]}]
set_property PULLTYPE PULLDOWN [get_ports {A[1]}]
set_property PULLTYPE PULLDOWN [get_ports {A[0]}]
set_property PULLTYPE PULLDOWN [get_ports {Y_low[7]}]
set_property PULLTYPE PULLDOWN [get_ports {Y_low[6]}]
set_property PULLTYPE PULLDOWN [get_ports {Y_low[5]}]
set_property PULLTYPE PULLDOWN [get_ports {Y_low[4]}]
set_property PULLTYPE PULLDOWN [get_ports {Y_low[3]}]
set_property PULLTYPE PULLDOWN [get_ports {Y_low[2]}]
set_property PULLTYPE PULLDOWN [get_ports {Y_low[1]}]
set_property PULLTYPE PULLDOWN [get_ports {Y_low[0]}]
set_property PULLTYPE PULLDOWN [get_ports E1]
set_property PULLTYPE PULLDOWN [get_ports E2_low]
set_property PULLTYPE PULLDOWN [get_ports E3_low]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property PACKAGE_PIN R1 [get_ports {Y_low[7]}]
set_property PACKAGE_PIN P2 [get_ports {Y_low[6]}]
set_property PACKAGE_PIN P1 [get_ports {Y_low[5]}]
set_property PACKAGE_PIN N2 [get_ports {Y_low[4]}]
set_property PACKAGE_PIN M1 [get_ports {Y_low[3]}]
set_property PACKAGE_PIN M2 [get_ports {Y_low[2]}]
set_property PACKAGE_PIN L1 [get_ports {Y_low[1]}]
set_property PACKAGE_PIN J2 [get_ports {Y_low[0]}]
set_property PACKAGE_PIN T3 [get_ports E1]
set_property PACKAGE_PIN U3 [get_ports E2_low]
set_property PACKAGE_PIN T4 [get_ports E3_low]
set_property PACKAGE_PIN V3 [get_ports {A[2]}]
set_property PACKAGE_PIN V4 [get_ports {A[1]}]
set_property PACKAGE_PIN W4 [get_ports {A[0]}]

仿真

`timescale 1ns / 1ps

module Decoder_Test;
  reg [2:0] A;
  reg E1, E2_low, E3_low;
  wire [7:0] Y_low;
  Decoder simu (
      A,
      E1,
      E2_low,
      E3_low,
      Y_low
  );
  initial begin
    E1 = 0;
    E2_low = 0;
    E3_low = 0;
    A = 3'b000;
    #100 E1 = 1;
    E2_low = 0;
    E3_low = 0;
    forever begin
      #100 A = A + 3'b001;
      if (A == 3'b111) $finish;
    end
  end
endmodule