*$
* TPS5430
*****************************************************************************
* (C) Copyright 2014 Texas Instruments Incorporated. All rights reserved.
*****************************************************************************
** This model is designed as an aid for customers of Texas Instruments.
** TI and its licensors and suppliers make no warranties, either expressed
** or implied, with respect to this model, including the warranties of
** merchantability or fitness for a particular purpose. The model is
** provided solely on an "as is" basis. The entire risk as to its quality
** and performance is with the customer
*****************************************************************************
*
* This model is subject to change without notice. Texas Instruments
* Incorporated is not responsible for updating this model.
*
*****************************************************************************
*
** Released by: Analog eLab Design Center, Texas Instruments Inc.
* Part: TPS5430
* Date: 08JUL2014
* Model Type: TRANSIENT
* Simulator: PSPICE
* Simulator Version: 16.2.0.p001
* EVM Order Number: TPS5430/31EVM-173
* EVM Users Guide: SLVU157 ?March 2006
* Datasheet: SLVS632E ?JANUARY 2006 ?REVISED SEPTEMBER 2013
*
* Model Version: Final 1.00
*
*****************************************************************************
*
* Updates:
*
* Final 1.00
* Release to Web.
*
*****************************************************************************
.SUBCKT TPS5430_TRANS BOOT ENA GND NC NC1 PAD PH VIN VSENSE params: MODE=0
R_U_ERROR_AMP_R3 EA_INT U_ERROR_AMP_N01952 3.27MEG TC=0,0
R_U_ERROR_AMP_R1 VSENSE U_ERROR_AMP_N01760 260k TC=0,0
C_U_ERROR_AMP_C2 U_ERROR_AMP_N01952 U_ERROR_AMP_N02024 30p TC=0,0
V_U_ERROR_AMP_V1 U_ERROR_AMP_N128290 GND 3.3Vdc
C_U_ERROR_AMP_C1 U_ERROR_AMP_N01760 U_ERROR_AMP_N02024 20p TC=0,0
R_U_ERROR_AMP_R2 VSENSE U_ERROR_AMP_N02024 2.75Meg TC=0,0
C_U_ERROR_AMP_C3 EA_INT U_ERROR_AMP_N02024 1p TC=0,0
X_U_ERROR_AMP_U1 REF_INT U_ERROR_AMP_N02024 U_ERROR_AMP_N128290 GND
+ EA_INT stdopamp PARAMS: GAIN=206.538K RIN=20MEG RINC=1E9 ROUT=1
+ SLEWRATE=1.5Meg FPOLE1=14.96 FPOLE2=10MEG VDROPOH=0 VDROPOL=0 VOFFS=0 IBIAS=0
+ IOFFS=0
R_U_PWM_GEN_R1 U_PWM_GEN_N03570 U_PWM_GEN_N14321964 1 TC=0,0
X_U_PWM_GEN_U1 EA_INT RAMP_INT U_PWM_GEN_N03570 COMP_BASIC_GEN PARAMS:
+ VDD=1 VSS=0 VTHRESH=0.5
C_U_PWM_GEN_C1 0 U_PWM_GEN_N14321964 1n TC=0,0
X_U_PWM_GEN_U10 U_PWM_GEN_N14321964 ENA_UVLO_INT PWM_INT AND2_BASIC_GEN
+ PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_D3 ENA VIN d_d2 PARAMS:
R_R_RESPADTOGND PAD GND 10M
G_U_HICCUP_G3 0 U_HICCUP_N14356275 U_HICCUP_N14356829 0 1
X_U_HICCUP_U621 U_HICCUP_N14356649 U_HICCUP_N14356641
+ U_HICCUP_N14356829 AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
C_U_HICCUP_C1 0 U_HICCUP_N14356275 50n IC=0
X_U_HICCUP_U610 U_HICCUP_N14356263 U_HICCUP_N14356397
+ INV_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY=100n
X_U_HICCUP_U617 ENA_UVLO U_HICCUP_N14357133 INV_DELAY_BASIC_GEN PARAMS:
+ VDD=1 VSS=0 VTHRESH=0.5 DELAY=500n
C_U_HICCUP_C6 0 U_HICCUP_N14356915 1n IC=0
C_U_HICCUP_C82 U_HICCUP_H_CHECK 0 2n IC=0
C_U_HICCUP_C4 0 U_HICCUP_N14356233 1n IC=0
X_U_HICCUP_U30 U_HICCUP_N14356257 U_HICCUP_RESET_LATCH
+ U_HICCUP_HICCUP_INT HICCUPB_INT srlatchrhp_basic_gen PARAMS: VDD=1 VSS=0
+ VTHRESH=0.5
X_U_HICCUP_U618 U_HICCUP_EN_UVLO_PULSE U_HICCUP_SLEEP_END_PULSE
+ U_HICCUP_RESET_LATCH OR2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_HICCUP_U625 U_HICCUP_ILIMIT_MASTER_PULSE U_HICCUP_N14357067
+ U_HICCUP_N14356547 U_HICCUP_N14356559 U_HICCUP_N14356981 U_HICCUP_VDC_1V
+ dffsbrb_rhpbasic_gen PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
V_U_HICCUP_V11 U_HICCUP_N14356427 0 25
G_U_HICCUP_ABMI5 U_HICCUP_N14357171 U_HICCUP_H_CHECK VALUE {
+ {(2e-9)*25*5e5/8000} }
V_U_HICCUP_V3 U_HICCUP_N14356319 0 5
X_U_HICCUP_U612 U_HICCUP_H_CHECK U_HICCUP_N14356427 U_HICCUP_N14356379
+ COMP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
X_U_HICCUP_U623 U_HICCUP_N14356795 U_HICCUP_N14356765
+ U_HICCUP_N14356835 AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_HICCUP_U619 U_HICCUP_N14356509 U_HICCUP_N14356981 INV_BASIC_GEN
+ PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_HICCUP_U620 U_HICCUP_HICCUP_INT_PULSE U_HICCUP_EN_UVLO_PULSE
+ U_HICCUP_N14356509 OR2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
V_U_HICCUP_V47 U_HICCUP_N14357171 0 30
X_U_HICCUP_S7 U_HICCUP_N14356835 0 U_HICCUP_N14356275 0 HICCUP_U_HICCUP_S7
X_U_HICCUP_U622 U_HICCUP_ILIMIT_MASTER_PULSE U_HICCUP_N14356765
+ INV_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
V_U_HICCUP_V10 U_HICCUP_N14356283 0 1.5
V_U_HICCUP_V15 U_HICCUP_VDC_1V 0 1
X_U_HICCUP_U611 U_HICCUP_N14356263 U_HICCUP_N14356397
+ U_HICCUP_SLEEP_END_PULSE AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_HICCUP_D13 U_HICCUP_H_CHECK U_HICCUP_N14357171 d_d2 PARAMS:
X_U_HICCUP_U12 CLK_INT U_HICCUP_N14356547 INV_DELAY_BASIC_GEN PARAMS:
+ VDD=1 VSS=0 VTHRESH=0.5 DELAY=1n
C_U_HICCUP_C5 0 U_HICCUP_N14356263 1n IC=0
X_U_HICCUP_U14 U_HICCUP_ILIMIT_MASTER_PULSE U_HICCUP_N14356795
+ BUF_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY=500n
X_U_HICCUP_D10 U_HICCUP_N14356275 U_HICCUP_N14356319 d_d2 PARAMS:
X_U_HICCUP_U608 U_HICCUP_N14356233 U_HICCUP_N14356173
+ U_HICCUP_HICCUP_INT_PULSE AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_HICCUP_U607 U_HICCUP_N14356233 U_HICCUP_N14356173
+ INV_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY=10u
R_U_HICCUP_R277 U_HICCUP_N14357067 U_HICCUP_N14356915 1
X_U_HICCUP_U13 ILIMIT_PULSE_INT U_HICCUP_N14356559 BUF_DELAY_BASIC_GEN
+ PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY=20n
R_U_HICCUP_R3 U_HICCUP_N14356263 U_HICCUP_N14356379 1
R_U_HICCUP_R2 U_HICCUP_N14356233 U_HICCUP_HICCUP_INT 1
X_U_HICCUP_U609 U_HICCUP_N14356275 U_HICCUP_N14356283
+ U_HICCUP_N14356257 COMP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
X_U_HICCUP_U624 ILIMIT_PULSE_INT U_HICCUP_N14356649 INV_BASIC_GEN
+ PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_HICCUP_U614 U_HICCUP_N14356649 U_HICCUP_N14356641
+ INV_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY=50n
X_U_HICCUP_S35 HICCUPB_INT 0 U_HICCUP_H_CHECK 0 HICCUP_U_HICCUP_S35
X_U_HICCUP_U613 ENA_UVLO U_HICCUP_N14357133 U_HICCUP_EN_UVLO_PULSE
+ AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
R_U_OVP_R1 U_OVP_N05674 U_OVP_N05387 1 TC=0,0
X_U_OVP_U10 U_OVP_N05387 ENA_UVLO_INT OVP_INT AND2_BASIC_GEN PARAMS:
+ VDD=1 VSS=0 VTHRESH=500E-3
R_U_OVP_R2 U_OVP_N04997 U_OVP_REF_IN_UP 1 TC=0,0
C_U_OVP_C1 GND U_OVP_N05387 1n TC=0,0
C_U_OVP_C2 GND U_OVP_REF_IN_UP 1n TC=0,0
X_U_OVP_U1 VSENSE U_OVP_REF_IN_UP U_OVP_N05674 COMP_BASIC_GEN PARAMS:
+ VDD=1 VSS=0 VTHRESH=0.5
E_U_OVP_E1 U_OVP_N04997 GND REF_INT GND 1.125
I_I1 VIN ENA DC 5uAdc
C_U_SOFT_START_C1 GND U_SOFT_START_REF_SLOW1_221_8MS 8u IC=0 TC=0,0
R_U_SOFT_START_R2 U_SOFT_START_N14296185 REF_INT 1 TC=0,0
V_U_SOFT_START_V2 U_SOFT_START_N143033081 U_SOFT_START_REF_1P221V 500m
E_U_SOFT_START_ABM4 U_SOFT_START_N14297002 0 VALUE { IF ((
+ V(ENA_UVLO_INT) >0.5 ), V(U_SOFT_START_REF_1P221V) , V(GND)) }
X_U_SOFT_START_S1 ENA_UVLO_INT GND U_SOFT_START_REF_SLOW1_221_8MS GND
+ SOFT_START_U_SOFT_START_S1
V_U_SOFT_START_V1 U_SOFT_START_REF_1P221V GND 1.221Vdc
I_U_SOFT_START_I1 GND U_SOFT_START_REF_SLOW1_221_8MS DC 1.221mAdc
D_U_SOFT_START_D3 U_SOFT_START_REF_SLOW1_221_8MS
+ U_SOFT_START_N143033081 D_D
E_U_SOFT_START_ABM1 U_SOFT_START_N14296271 0 VALUE { IF ((
+ V(U_SOFT_START_REF_SLOW1_221_8MS) <V(U_SOFT_START_REF_1P221V) ),
+ V(U_SOFT_START_REF_SLOW1_221_8MS) , V(U_SOFT_START_REF_1P221V)) }
C_U_SOFT_START_C2 GND REF_INT 1n TC=0,0
E_U_SOFT_START_ABM2 U_SOFT_START_N14296185 0 VALUE { IF (( {MODE} <0.5
+ ), V(U_SOFT_START_N14296271) , V(U_SOFT_START_N14297002)) }
V_U_ENA_UVLO_V5 U_ENA_UVLO_N02651 0 1.15
X_U_ENA_UVLO_U11 ENA_UVLO HICCUPB_INT ENA_UVLO_INT AND2_BASIC_GEN
+ PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
V_U_ENA_UVLO_V6 U_ENA_UVLO_N02659 0 0.45
V_U_ENA_UVLO_V3 U_ENA_UVLO_N02384 0 5.3
V_U_ENA_UVLO_V4 U_ENA_UVLO_N02391 0 330m
X_U_ENA_UVLO_U8 VIN U_ENA_UVLO_N02384 U_ENA_UVLO_N02391
+ U_ENA_UVLO_UVLO_INT COMPHYS_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
X_U_ENA_UVLO_U6 U_ENA_UVLO_UVLO_INT U_ENA_UVLO_ENA_INT ENA_UVLO
+ AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_ENA_UVLO_U9 ENA U_ENA_UVLO_N02651 U_ENA_UVLO_N02659
+ U_ENA_UVLO_ENA_INT COMPHYS_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
D_U_DIG_LOGIC_D3 U_DIG_LOGIC_ILIMIT_DELAYED ILIMIT_INT D_D
R_U_DIG_LOGIC_R2 U_DIG_LOGIC_N06802 U_DIG_LOGIC_N06762 11.6k TC=0,0
X_U_DIG_LOGIC_U3 U_DIG_LOGIC_PWM_OVP_IN U_DIG_LOGIC_DCYCLE_AND_ILIMIT
+ U_DIG_LOGIC_N14337715 AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_DIG_LOGIC_U8 U_DIG_LOGIC_Q_ILIMIT U_DIG_LOGIC_QB U_DIG_LOGIC_VDC_1V
+ U_DIG_LOGIC_VDC_1V CLK_INT U_DIG_LOGIC_ILIMIT_FINAL dffsbrb_rhpbasic_gen
+ PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_DIG_LOGIC_U16 U_DIG_LOGIC_N08093 ENA_UVLO_INT PWM_PFET_INT
+ AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_DIG_LOGIC_U6 U_DIG_LOGIC_N14296672 CLK_INT
+ U_DIG_LOGIC_DCYCLE_AND_ILIMIT AND2_BASIC_GEN PARAMS: VDD=1 VSS=0
+ VTHRESH=500E-3
R_U_DIG_LOGIC_R3 GND U_DIG_LOGIC_N14337691 1M TC=0,0
X_U_DIG_LOGIC_U10 OVP_INT U_DIG_LOGIC_N14327543 INV_DELAY_BASIC_GEN
+ PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY=10n
E_U_DIG_LOGIC_ABM2 U_DIG_LOGIC_N14330255 0 VALUE { IF (
+ (V(CONS_RAMP_INT) < 0.8344) , 1 , 0 ) }
V_U_DIG_LOGIC_V3 U_DIG_LOGIC_VDC_1V GND 1
X_U_DIG_LOGIC_U15 CLK_INT U_DIG_LOGIC_N14336173 U_DIG_LOGIC_LATCH_CLK
+ AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
C_U_DIG_LOGIC_C1 GND U_DIG_LOGIC_ILIMIT_DELAYED 10p TC=0,0
C_U_DIG_LOGIC_C2 GND U_DIG_LOGIC_N06762 10p TC=0,0
X_U_DIG_LOGIC_U11 PWM_INT U_DIG_LOGIC_N14327543 U_DIG_LOGIC_PWM_OVP_IN
+ AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_DIG_LOGIC_U7 U_DIG_LOGIC_N06622 U_DIG_LOGIC_N06762
+ U_DIG_LOGIC_N08093 OR2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=300E-3
X_U_DIG_LOGIC_U9 ILIMIT_PULSE_INT U_DIG_LOGIC_N14296672
+ U_DIG_LOGIC_Q_ILIMIT CLK_INT CLK_INT U_DIG_LOGIC_VDC_1V dffsbrb_rhpbasic_gen
+ PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_DIG_LOGIC_U13 U_DIG_LOGIC_N14330255 ENA_UVLO_INT CLK_INT
+ AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
R_U_DIG_LOGIC_R6 GND U_DIG_LOGIC_QB 1k TC=0,0
X_U_DIG_LOGIC_U2 U_DIG_LOGIC_LATCH_CLK U_DIG_LOGIC_N14337711
+ U_DIG_LOGIC_N06622 U_DIG_LOGIC_N14337691 srlatchrhp_basic_gen PARAMS: VDD=1
+ VSS=0 VTHRESH=0.5
X_U_DIG_LOGIC_U5 U_DIG_LOGIC_N06657 U_DIG_LOGIC_N06622
+ U_DIG_LOGIC_N06802 AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_DIG_LOGIC_U14 CLK_INT U_DIG_LOGIC_N14336173 INV_DELAY_BASIC_GEN
+ PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY=10n
R_U_DIG_LOGIC_R1 ILIMIT_INT U_DIG_LOGIC_ILIMIT_DELAYED 8.5k TC=0,0
D_U_DIG_LOGIC_D2 U_DIG_LOGIC_N06802 U_DIG_LOGIC_N06762 D_D
X_U_DIG_LOGIC_U12 U_DIG_LOGIC_N14337715 U_DIG_LOGIC_N14337711
+ INV_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_DIG_LOGIC_U4 U_DIG_LOGIC_N06622 U_DIG_LOGIC_N06657
+ INV_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY=10n
X_U_DIG_LOGIC_U1 ILIMIT_INT U_DIG_LOGIC_ILIMIT_DELAYED
+ U_DIG_LOGIC_ILIMIT_FINAL NAND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
C_U_PFET_ILIMIT_C2 0 ILIMIT_INT 1n TC=0,0
X_U_PFET_ILIMIT_S1 PWM_PFET_INT 0 VIN U_PFET_ILIMIT_N02026
+ PFET_ILIMIT_U_PFET_ILIMIT_S1
R_U_PFET_ILIMIT_R2 U_PFET_ILIMIT_N14292796 ILIMIT_INT 1 TC=0,0
X_U_PFET_ILIMIT_S2 ENA_UVLO_INT 0 U_PFET_ILIMIT_N14291358 PH
+ PFET_ILIMIT_U_PFET_ILIMIT_S2
V_U_PFET_ILIMIT_V1 U_PFET_ILIMIT_N142919940 U_PFET_ILIMIT_N02026 8
X_U_PFET_ILIMIT_D1 U_PFET_ILIMIT_N02026 VIN d_d2 PARAMS:
E_U_PFET_ILIMIT_ABM1 U_PFET_ILIMIT_N14292796 0 VALUE { IF (
+ V(U_PFET_ILIMIT_VILIMIT_SIG) > 5,1,0 ) }
X_U_PFET_ILIMIT_S3 ENA_UVLO_INT 0 PH 0 PFET_ILIMIT_U_PFET_ILIMIT_S3
R_U_PFET_ILIMIT_R1 BOOT U_PFET_ILIMIT_N142919940 50 TC=0,0
X_U_PFET_ILIMIT_H1 U_PFET_ILIMIT_N02026 U_PFET_ILIMIT_N14291358
+ U_PFET_ILIMIT_VILIMIT_SIG 0 PFET_ILIMIT_U_PFET_ILIMIT_H1
E_U_RAMP_GEN_ABM3 CONS_RAMP_INT 0 VALUE { if( V(ENA_UVLO_INT) > 0.5,
+ v(U_RAMP_GEN_N04726) , 0) }
E_U_RAMP_GEN_ABM4 RAMP_INT 0 VALUE { ((V(CONS_RAMP_INT)*V(VIN)/25)+0.3)
+ }
V_U_RAMP_GEN_V2 U_RAMP_GEN_N04726 GND DC 0
+PULSE 0 0.9375 0 1.999u 1n 0 2u
.IC V(EA_INT )={MODE*0.505}
.ENDS TPS5430_TRANS
*$
.subckt HICCUP_U_HICCUP_S7 1 2 3 4
S_U_HICCUP_S7 3 4 1 2 _U_HICCUP_S7
RS_U_HICCUP_S7 1 2 1G
.MODEL _U_HICCUP_S7 VSWITCH Roff=1e9 Ron=1.0m Voff=0.25 Von=0.75
.ends HICCUP_U_HICCUP_S7
*$
.subckt HICCUP_U_HICCUP_S35 1 2 3 4
S_U_HICCUP_S35 3 4 1 2 _U_HICCUP_S35
RS_U_HICCUP_S35 1 2 1G
.MODEL _U_HICCUP_S35 VSWITCH Roff=1e12 Ron=1.0m Voff=0.4V Von=0.5V
.ends HICCUP_U_HICCUP_S35
*$
.subckt SOFT_START_U_SOFT_START_S1 1 2 3 4
S_U_SOFT_START_S1 3 4 1 2 _U_SOFT_START_S1
RS_U_SOFT_START_S1 1 2 1G
.MODEL _U_SOFT_START_S1 VSWITCH Roff=1.0m Ron=1e9 Voff=200m Von=300m
.ends SOFT_START_U_SOFT_START_S1
*$
.subckt PFET_ILIMIT_U_PFET_ILIMIT_S1 1 2 3 4
S_U_PFET_ILIMIT_S1 3 4 1 2 _U_PFET_ILIMIT_S1
RS_U_PFET_ILIMIT_S1 1 2 1G
.MODEL _U_PFET_ILIMIT_S1 VSWITCH Roff=10e6 Ron=110m Voff=0.2V Von=0.8V
.ends PFET_ILIMIT_U_PFET_ILIMIT_S1
*$
.subckt PFET_ILIMIT_U_PFET_ILIMIT_S2 1 2 3 4
S_U_PFET_ILIMIT_S2 3 4 1 2 _U_PFET_ILIMIT_S2
RS_U_PFET_ILIMIT_S2 1 2 1G
.MODEL _U_PFET_ILIMIT_S2 VSWITCH Roff=1e9 Ron=0.1m Voff=0.2 Von=0.8
.ends PFET_ILIMIT_U_PFET_ILIMIT_S2
*$
.subckt PFET_ILIMIT_U_PFET_ILIMIT_S3 1 2 3 4
S_U_PFET_ILIMIT_S3 3 4 1 2 _U_PFET_ILIMIT_S3
RS_U_PFET_ILIMIT_S3 1 2 1G
.MODEL _U_PFET_ILIMIT_S3 VSWITCH Roff=10m Ron=1e9 Voff=0.2 Von=0.8
.ends PFET_ILIMIT_U_PFET_ILIMIT_S3
*$
.subckt PFET_ILIMIT_U_PFET_ILIMIT_H1 1 2 3 4
H_U_PFET_ILIMIT_H1 3 4 VH_U_PFET_ILIMIT_H1 1
VH_U_PFET_ILIMIT_H1 1 2 0V
.ends PFET_ILIMIT_U_PFET_ILIMIT_H1
*$
.subckt stdopamp inp inm vdd vss out
+ params: gain=206k rin=20meg rinc=1e9 rout=1 slewrate=1.5meg fpole1=14.96meg
+ fpole2=10meg
+ vdropoh=0 vdropol=0 voffs=0 ibias=0 ioffs=0
.param vosw = 15
.param pi = 3.141592
.param is = 8.0e-16
.param vt = 0.02585
.param c1 = {vosw/rout/slewrate}
.param imax = {c1*slewrate}
.param r1 = {1/(2*pi*c1*fpole1)}
.param gm1 = {gain/r1}
.param r2 = 100
.param g2 = {1/r2}
.param gout = {1/rout}
.param c2 = {1/(2*pi*r2*fpole2)}
.param vdf = {vt*log(1 + imax/is)}
ibiasm inm 0 {ibias - ioffs}
rinm inm 8 {2*rinc}
rinp inp 8 {2*rinc}
ibias 10 0 {ibias}
voffs 10 inp {voffs}
evdd vddi 0 vdd 0 1
evss vssi 0 vss 0 1
vc vddi 11 {vdropoh + vdf}
ve 12 vssi {vdropol + vdf}
d1 vss vdd d_1
rp vdd vss 15e3
rout out 8 {rout}
gmo 8 out value = {v(9,8)*gout}
c2 9 8 {c2}
r2 9 8 {r2}
gm2 8 9 value = {v(7,8)*g2}
rin inm 10 {rin}
egnd 8 0 poly(2) (vdd,0) (vss,0) 0 .5 .5
d3 12 7 d_1
d2 7 11 d_1
c1 7 8 {c1}
r1 7 8 {r1}
gm1 8 7 value = { limit( gm1*v(10,inm), -imax, imax) }
.model d_1 d
+ rs=0.01
.ends
*$
.subckt d_d2 1 2
d1 1 2 dd1
.model dd1 d
+ is=1e-015
+ tt=1e-011
+ rs=0.05
+ n=0.1
.ends d_d2
*$
.subckt srlatchrhp_basic_gen s r q qb params: vdd=1 vss=0 vthresh=0.5
gq 0 qint value = {if(v(r) > {vthresh},-5,if(v(s)>{vthresh},5, 0))}
cqint qint 0 1n
rqint qint 0 1000meg
d_d10 qint my5 d_d1
v1 my5 0 {vdd}
d_d11 myvss qint d_d1
v2 myvss 0 {vss}
eq qqq 0 qint 0 1
x3 qqq qqqd1 buf_basic_gen params: vdd={vdd} vss={vss} vthresh={vthresh}
rqq qqqd1 q 1
eqb qbr 0 value = {if( v(q) > {vthresh}, {vss},{vdd})}
rqb qbr qb 1
cdummy1 q 0 1n
cdummy2 qb 0 1n
.ic v(qint) {vss}
.model d_d1 d
+ is=1e-015
+ tt=1e-011
+ rs=0.005
+ n=0.1
.ends srlatchrhp_basic_gen
*$
.subckt dffsbrb_rhpbasic_gen q qb clk d rb sb params: vdd=1 vss=0 vthresh=0.5
x1 clk clkdel1 inv_basic_gen params: vdd={vdd} vss={vss} vthresh={vthresh}
r_clk clkdel1 clkdel 21.64502165
c_clk clkdel 0 1n
x2 clk clkdel clkint and2_basic_gen params: vdd={vdd} vss={vss} vthresh=
+ {vthresh}
gq 0 qint value = {if(v(rb) < {vthresh},-5,if(v(sb)< {vthresh},5,
+ if(v(clkint)> {vthresh},
+ if(v(d)> {vthresh},5,-5),0)))}
cqint qint 0 1n
rqint qint 0 1000meg
d_d10 qint my5 d_d1
v1 my5 0 5
d_d11 0 qint d_d1
eq qqq 0 qint 0 1
x3 qqq qqqd1 buf_delay_basic_gen params: vdd={vdd} vss={vss} vthresh={vthresh}
+ delay = 1n
rqq qqqd1 q 1
eqb qbr 0 value = {if( v(q) > {vthresh}, {vss},{vdd})}
rqb qbr qb 1
cdummy1 q 0 1nf
cdummy2 qb 0 1nf
.ic v(qint) {vss}
.model d_d1 d
+ is=1e-015
+ tt=1e-011
+ rs=0.05
+ n=0.1
.ends dffsbrb_rhpbasic_gen
*$
.model D_D d
+ is=1e-015
+ n=0.0001
+ tt=1e-011
+ rs=0.05
*$
.SUBCKT CESR IN OUT
+ PARAMs: C=100u ESR=0.01 X=2 IC=0
C IN 1 {C*X} IC={IC}
RESR 1 OUT {ESR/X}
.ENDS CESR
*$
.SUBCKT LDCR IN OUT
+ PARAMs: L=1u DCR=0.01 IC=0
L IN 1 {L} IC={IC}
RDCR 1 OUT {DCR}
.ENDS LDCR
*$
.SUBCKT INV_BASIC_GEN A Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} ,
+ {VSS},{VDD})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS INV_BASIC_GEN
*$
.SUBCKT INV_DELAY_BASIC_GEN A Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY = 10n
E_ABMGATE1 YINT1 0 VALUE {{IF(V(A) > {VTHRESH} ,
+ {VDD},{VSS})}}
RINT YINT1 YINT2 1
CINT YINT2 0 {DELAY*1.3}
E_ABMGATE2 YINT3 0 VALUE {{IF(V(YINT2) > {VTHRESH} ,
+ {VSS},{VDD})}}
RINT2 YINT3 Y 1
CINT2 Y 0 1n
.ENDS INV_DELAY_BASIC_GEN
*$
.SUBCKT BUF_BASIC_GEN A Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} ,
+ {VDD},{VSS})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS BUF_BASIC_GEN
*$
.SUBCKT AND2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} &
+ V(B) > {VTHRESH},{VDD},{VSS})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS AND2_BASIC_GEN
*$
.SUBCKT BUF_DELAY_BASIC_GEN A Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY = 10n
E_ABMGATE1 YINT1 0 VALUE {{IF(V(A) > {VTHRESH} ,
+ {VDD},{VSS})}}
RINT YINT1 YINT2 1
CINT YINT2 0 {DELAY*1.3}
E_ABMGATE2 YINT3 0 VALUE {{IF(V(YINT2) > {VTHRESH} ,
+ {VDD},{VSS})}}
RINT2 YINT3 Y 1
CINT2 Y 0 1n
.ENDS BUF_DELAY_BASIC_GEN
*$
.SUBCKT NAND2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} &
+ V(B) > {VTHRESH},{VSS},{VDD})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS NAND2_BASIC_GEN
*$
.SUBCKT OR2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} |
+ V(B) > {VTHRESH},{VDD},{VSS})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS OR2_BASIC_GEN
*$
.SUBCKT COMP_BASIC_GEN INP INM Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
E_ABM Yint 0 VALUE {IF (V(INP) >
+ V(INM), {VDD},{VSS})}
R1 Yint Y 1
C1 Y 0 1n
.ENDS COMP_BASIC_GEN
*$
.SUBCKT COMPHYS_BASIC_GEN INP INM HYS OUT PARAMS: VDD=1 VSS=0 VTHRESH=0.5
EIN INP1 INM1 INP INM 1
EHYS INP1 INP2 VALUE { IF( V(1) > {VTHRESH},-V(HYS),0) }
EOUT OUT 0 VALUE { IF( V(INP2)>V(INM1), {VDD} ,{VSS}) }
R1 OUT 1 1
C1 1 0 5n
RINP1 INP1 0 1K
.ENDS COMPHYS_BASIC_GEN
*$
.model D_D1 d
+ is=1e-015
+ tt=1e-011
+ rs=0.05
+ n=0.1
*$
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