<?xml version="1.0" encoding="utf-8" ?><rss version="2.0"><channel><title><![CDATA[HelloQili的博客]]></title><description><![CDATA[]]></description><link>https://blog.youkuaiyun.com/HelloQili</link><language>zh-cn</language><generator>https://blog.youkuaiyun.com/</generator><copyright><![CDATA[Copyright &copy; HelloQili]]></copyright><item><title><![CDATA[SDF延时文件中为什么会有负延时？]]></title><link>https://blog.youkuaiyun.com/HelloQili/article/details/129155337</link><guid>https://blog.youkuaiyun.com/HelloQili/article/details/129155337</guid><author>HelloQili</author><pubDate>Wed, 22 Feb 2023 09:22:08 +0800</pubDate><description><![CDATA[也就是在电平transition时，transition的start肯定是output晚于input的，但是output可能会比input先达到阈值电压，从而构成了负的cell delay.]]></description><category></category></item><item><title><![CDATA[【原创】关于后仿我知道的不多]]></title><link>https://blog.youkuaiyun.com/HelloQili/article/details/129128625</link><guid>https://blog.youkuaiyun.com/HelloQili/article/details/129128625</guid><author>HelloQili</author><pubDate>Mon, 20 Feb 2023 17:38:35 +0800</pubDate><description><![CDATA[GLS 后仿]]></description><category></category></item><item><title><![CDATA[PCIe协议学习笔记之--Configuration Overview]]></title><link>https://blog.youkuaiyun.com/HelloQili/article/details/112392043</link><guid>https://blog.youkuaiyun.com/HelloQili/article/details/112392043</guid><author>HelloQili</author><pubDate>Wed, 12 Jan 2022 10:57:05 +0800</pubDate><description><![CDATA[1 BDF (Bus, Device, Function)

BDF是在PCI中就有了的概念。在PCIe 拓扑结构中，我们通过总线号(bus number), 设备号(device numer)和功能号(function number)来唯一地标识各个function。Bus number用于表征当前设备挂载于哪条bus下面，Device number用于表征设备具体是总线下的哪个设备，function number用于表征是device里面的哪个function。



如上例图，从bus 0开始，每经过]]></description><category></category></item><item><title><![CDATA[VCS仿真性能优化]]></title><link>https://blog.youkuaiyun.com/HelloQili/article/details/122101633</link><guid>https://blog.youkuaiyun.com/HelloQili/article/details/122101633</guid><author>HelloQili</author><pubDate>Thu, 23 Dec 2021 10:44:09 +0800</pubDate><description><![CDATA[1 热点分析
编译选项 -simprofile
1.Compile your design using the -simprofile compile-time option.Important:If this is not the first compilation of your design, delete the csrc and simv.daidir directories and simv executable file before this step. Incremental compil]]></description><category></category></item><item><title><![CDATA[【转】静态时序分析之恢复时间recovery time和撤销时间removal time]]></title><link>https://blog.youkuaiyun.com/HelloQili/article/details/121037030</link><guid>https://blog.youkuaiyun.com/HelloQili/article/details/121037030</guid><author>HelloQili</author><pubDate>Fri, 29 Oct 2021 16:11:04 +0800</pubDate><description><![CDATA[1、概念 
同步电路中，输入数据需要与时钟满足setup time和hold time才能进行数据的正常传输，防止亚稳态； 
类似的，对于一个异步复位寄存器来说，置位和复位信号同样需要和时钟满足recovery time和removal time才能有效进行置位和复位操作。 
 
recovery time：恢复时间。撤销复位时，恢复到非复位状态的电平必须在时钟有效沿到来之前的一段时间到来，才能保证时钟能有效恢复到...]]></description><category></category></item><item><title><![CDATA[VC Formal FPV 启动脚本简单模板]]></title><link>https://blog.youkuaiyun.com/HelloQili/article/details/120767408</link><guid>https://blog.youkuaiyun.com/HelloQili/article/details/120767408</guid><author>HelloQili</author><pubDate>Thu, 14 Oct 2021 17:02:37 +0800</pubDate><description><![CDATA[VC Formal(下简称VCF)工具是Synopsys厂开发的一个用于静态分析验证的商业EDA工具。

VCF有很多种应用模式，比如FRV(Formal Register Verification), FPV(Formal Property Verification), FCA(Formal Coverage Analysis), SEQ(Sequential Equivalence Checking)等等。

本文主要介绍FPV的启动脚本。FPV是基于断言属性的静态检查。相对于动态仿真验证，其优势在于能]]></description><category></category></item><item><title><![CDATA[CXL初探，why CXL?]]></title><link>https://blog.youkuaiyun.com/HelloQili/article/details/120682926</link><guid>https://blog.youkuaiyun.com/HelloQili/article/details/120682926</guid><author>HelloQili</author><pubDate>Sun, 10 Oct 2021 15:00:58 +0800</pubDate><description><![CDATA[CPU适合做控制密集型的任务，并不擅长进行大量的数据计算，因此现在主流的技术方案都是通过总线将加速器与CPU连接起来，CPU将计算任务提交给加速器，加速器完成计算后将计算结果返回给CPU。这里的加速器，可以是GPGPU, 可以是深度学习ASIC，也可以是FPGA之类的，总之就是专门为并行计算而生的数据计算引擎。如今许多与AI相关的芯片公司都是做这个的。

CPU与加速器是怎么连接的呢？ PCIe总线！

CPU与加速器之间的数据交互大致是怎么进行的呢？

大致是基于Producer-Consumer模型，C]]></description><category></category></item><item><title><![CDATA[扔鸡蛋问题]]></title><link>https://blog.youkuaiyun.com/HelloQili/article/details/117529680</link><guid>https://blog.youkuaiyun.com/HelloQili/article/details/117529680</guid><author>HelloQili</author><pubDate>Sun, 22 Aug 2021 10:56:35 +0800</pubDate><description><![CDATA[状态方程：

F(N,M) = Min{ Max[F(N-1, k-1), F(N, M-k)] }


import numpy as np

def throw_egg(num_egg, num_floor):
	rslt_list=np.zeros((num_egg+1, num_floor+1), dtype=int)
	for in in range(1, num_floor+1):
	    rslt_list[1][i] = i

	if (num_egg &lt; 2):
		return ]]></description><category></category></item><item><title><![CDATA[细说systemverilog @event与wait(event.triggered)的区别]]></title><link>https://blog.youkuaiyun.com/HelloQili/article/details/119356725</link><guid>https://blog.youkuaiyun.com/HelloQili/article/details/119356725</guid><author>HelloQili</author><pubDate>Tue, 03 Aug 2021 19:11:12 +0800</pubDate><description><![CDATA[近日在工作中遇到了@event和wait(event.triggered)的细微差别。与周边同事讨论了一圈，发现大家都貌似懂他们的区别，但都无法特别严谨细致地进行解释。

针对这种语法上的细节，建议直接从LRM原文着手。下面是相关的原文



1. @会阻塞一个进程，直到@的事件被触发(-&gt;)后，该进程才会unblock。如果事件触发(-&gt;event)在@event先执行，则@event的进程会一直被阻塞住。如果-&gt;event和@event发生在同一个time step，就会造成竞争冒险，]]></description><category></category></item><item><title><![CDATA[PCIe协议学习之-Ack/Nak协议]]></title><link>https://blog.youkuaiyun.com/HelloQili/article/details/115737108</link><guid>https://blog.youkuaiyun.com/HelloQili/article/details/115737108</guid><author>HelloQili</author><pubDate>Wed, 05 May 2021 21:44:50 +0800</pubDate><description><![CDATA[Ack/Nak协议是PCIe Data Link layer中最重要的内容。它用来保证TLP的可靠传输。它是基于Retry buffer实现的，Tx发出TLP后，将原始的TLP存到Retry buffer里面，当RX通过Ack DLLP告知已经正确收到TLP后才会将TLP中相应的TLP移除。当Rx通过Nak DLLP告知Tx有TLP出现错误后，Tx可以将Retry buffer中的相应TLP resent出去。

Tx和Rx的逻辑框图如下：



TX端

1）SEQ Num分配

DL层从TL层收到TLP]]></description><category></category></item><item><title><![CDATA[使用uvm_report_catcher屏蔽掉特定的uvm_error/uvm_warning]]></title><link>https://blog.youkuaiyun.com/HelloQili/article/details/113863561</link><guid>https://blog.youkuaiyun.com/HelloQili/article/details/113863561</guid><author>HelloQili</author><pubDate>Fri, 19 Feb 2021 15:14:43 +0800</pubDate><description><![CDATA[问题：

在一些异常case或者特殊的case, 遇到VIP报uvm_error或者uvm_warning,导致刷屏或者uvm_error数量达到上限仿真强制退出了。这时，可以用uvm_report_catcher捕获到它特定的message,并将其级别设置成UVM_INFO。

措施：

  uvm_report_cacherprovides the catch() function for users to extend.

 Return action_e type enum - - ...]]></description><category></category></item><item><title><![CDATA[gvim tags如何支持systemverilog]]></title><link>https://blog.youkuaiyun.com/HelloQili/article/details/113739550</link><guid>https://blog.youkuaiyun.com/HelloQili/article/details/113739550</guid><author>HelloQili</author><pubDate>Sun, 07 Feb 2021 16:05:03 +0800</pubDate><description><![CDATA[1 tags文件的格式

在gvim中敲:help tag可以查看tag的介绍，里面讲了tags的文件格式。

The first lines in the tags file can contain lines that start with
 !_TAG_
These are sorted to the first lines, only rare tags that start with "!" can
sort to before them. Vim recognizes two items...]]></description><category></category></item><item><title><![CDATA[芯片设计中常用到的调度算法总结]]></title><link>https://blog.youkuaiyun.com/HelloQili/article/details/112360184</link><guid>https://blog.youkuaiyun.com/HelloQili/article/details/112360184</guid><author>HelloQili</author><pubDate>Sat, 09 Jan 2021 11:27:55 +0800</pubDate><description><![CDATA[1 SP(Strict Priority, 严格优先级)

SP调度会给各个输入队列分配优先级，当高优先级的队列非空时，优先调度高优先级队列。只有当高优先级队列为空时，才有可能调度低优先级的队列。

2 RR(Round Robin, 轮询)

如何理解轮询？所谓‘轮’，是指RR调度中有一个RR指针，每次调度成功后，RR指针就会移动一下，指向下一个队列，而且这个指针是依次循环的，比如从0,1...一直到N，最后又循环到0。所谓'询'，就是指每次调度时去看RR指针指向的队列是否可用，如果可用的话，就调度RR指]]></description><category></category></item><item><title><![CDATA[UVM源码分析之factory机制详解]]></title><link>https://blog.youkuaiyun.com/HelloQili/article/details/112131514</link><guid>https://blog.youkuaiyun.com/HelloQili/article/details/112131514</guid><author>HelloQili</author><pubDate>Sun, 03 Jan 2021 15:57:31 +0800</pubDate><description><![CDATA[前言

作者在学习了一段时间的UVM factory源码之后写下此文，旨在记录自己的学习成果，毕竟好记性不如烂笔头嘛，当然如果能帮助到对这部分有疑惑的同仁就更好了。作者是在笔记本电脑上的windows环境下使用source insight软件分析UVM 源码的。感兴趣的同仁可以试试用source insight分析源码,个人认为还是比在纯编辑器(比如vim)方便很多。source insight支持systemverilog的配置文件可以通过https://download.youkuaiyun.com/downlo.]]></description><category></category></item><item><title><![CDATA[systemverilog中的时间单位和时间精度]]></title><link>https://blog.youkuaiyun.com/HelloQili/article/details/110438567</link><guid>https://blog.youkuaiyun.com/HelloQili/article/details/110438567</guid><author>HelloQili</author><pubDate>Tue, 01 Dec 2020 16:33:15 +0800</pubDate><description><![CDATA[1. `timescale

`timescale是systemverilog/verilog的预编译指令。指定位于该语句后面的time scope (module/program/package/interface等等）的时间单位和时间精度。直到遇到新的`timescale指令或者`resetall指令。

2.timeunit和timeprecision

timeunit关键字用于指定当前time scope的时间单位，timepresision用于指定当前time scope的时间精度。他们的作用.]]></description><category></category></item><item><title><![CDATA[芯片验证过程中代码覆盖率和功能覆盖率一高一低意味着什么？]]></title><link>https://blog.youkuaiyun.com/HelloQili/article/details/109632742</link><guid>https://blog.youkuaiyun.com/HelloQili/article/details/109632742</guid><author>HelloQili</author><pubDate>Wed, 11 Nov 2020 22:40:53 +0800</pubDate><description><![CDATA[在芯片验证岗位的面试过程中，有很多面试官喜欢问这个问题，目的是为了考察面试者对CDV(Coverage Drive Verification)的理解。本文讨论下这个问题。

1.代码覆盖率低 +功能覆盖率高

 1.1）有可能是cover group写得不完备，进一步地，测试点分解和test plan可能也不完备，尤其是对于初学者而言。遇到这种现象，PL应当警觉，需要明确是否存在测试点，test plan, cover group不完备的情况。

 1.2）DUT中有大量冗余代码。或者集成进来的公...]]></description><category></category></item><item><title><![CDATA[uvm启动过程及phase机制实现原理介绍]]></title><link>https://blog.youkuaiyun.com/HelloQili/article/details/109366552</link><guid>https://blog.youkuaiyun.com/HelloQili/article/details/109366552</guid><author>HelloQili</author><pubDate>Sat, 31 Oct 2020 16:24:10 +0800</pubDate><description><![CDATA[我们通常会在top写下类似下面的代码


module top（）;
    import uvm_pkg::*;
 
    ......
    initial begin
         run_test();
    end
    ......
endmoudle


]]></description><category></category></item><item><title><![CDATA[VCS使用问题记录]]></title><link>https://blog.youkuaiyun.com/HelloQili/article/details/109129493</link><guid>https://blog.youkuaiyun.com/HelloQili/article/details/109129493</guid><author>HelloQili</author><pubDate>Sat, 17 Oct 2020 10:13:00 +0800</pubDate><description><![CDATA[1. simulation报错

Error-[DPI-DIFNF] DPI import function not found

/opt/Synopsys/VCS2014/etc/uvm/base/uvm_resource.svh, 390

 The definition of DPI import function/task 'uvm_glob_to_re' does not exist.

 Please check the stated DPI import function/task is..]]></description><category></category></item><item><title><![CDATA[systemverilog package的作用以及include和import的区别]]></title><link>https://blog.youkuaiyun.com/HelloQili/article/details/108690990</link><guid>https://blog.youkuaiyun.com/HelloQili/article/details/108690990</guid><author>HelloQili</author><pubDate>Sun, 20 Sep 2020 11:27:09 +0800</pubDate><description><![CDATA[1. SV package 作用

sv中的package与c++中的namespace类似，都是为了解决命名冲突的问题。不同package里面的内容是可以重名的。使用时加pkg_name::xxx来指定用哪个pkg_name里面的xxx。

The package declaration creates a scope that contains declarations intended to be shared among one or
more compilation units, modules,]]></description><category></category></item><item><title><![CDATA[systemverilog中的wait fork和disable语句用法]]></title><link>https://blog.youkuaiyun.com/HelloQili/article/details/106481321</link><guid>https://blog.youkuaiyun.com/HelloQili/article/details/106481321</guid><author>HelloQili</author><pubDate>Wed, 10 Jun 2020 20:59:53 +0800</pubDate><description><![CDATA[disable语句用于在多进程的场景下终止一个或多个进程。
]]></description><category></category></item></channel></rss>