HDLBits学习笔记——状态机（上）

状态机这章题目比较多，分个小章节记录一下。

1.Simple FSM1

题目：

This is a Moore state machine with two states, one input, and one output. Implement this state machine. Notice that the reset state is B.

This exercise is the same as fsm1s, but using asynchronous reset.

思路：

第一题用来熟悉摩尔状态机的写法，题目把组合逻辑模块和时序逻辑模块都给好了，往里面填东西就行了。

代码：

module top_module(
    input clk,
    input areset,    // Asynchronous reset to state B
    input in,
    output out);//  

    parameter A=0, B=1; 
    reg state, next_state;

    always @(*) begin    // This is a combinational always block
        // State transition logic
        case({state,in})
            A：next_state = in ? A:B;
            B: next_steta = in ? B:A;
        endcase
    end

    always @(posedge clk, posedge areset) begin    // This is a sequential always block
        // State flip-flops with asynchronous reset
        if(areset)
            state <= B;
        else
            state <= next_state;
            
    end

    // Output logic
    // assign out = (state == ...);
	assign out = (state==B);
endmodule

组合模块用来更新下一个状态，时序模块用来复位以及给更新当前状态。

Moore状态机的输出只由当前状态决定，与输入无关。

Mealy状态机的输出与当前状态和输入均有关。

2.Simple FSM1

题目：

This is a Moore state machine with two states, one input, and one output. Implement this state machine. Notice that the reset state is B.

This exercise is the same as fsm1, but using synchronous reset.

思路：

与题1类似，不同的是本题改为同步复位。而且题目给的模板是一段式。

代码：

// Note the Verilog-1995 module declaration syntax here:
module top_module(clk, reset, in, out);
    input clk;
    input reset;    // Synchronous reset to state B
    input in;
    output out;//  
    reg out;

    // Fill in state name declarations
	parameter A=0,B=1;
    reg present_state, next_state;

    always @(posedge clk) begin
        if (reset) begin  
            // Fill in reset logic
            present_state <= B;
            out <= 1;
        end else begin
            case (present_state)
                // Fill in state transition logic
                A: next_state = in ? A:B;
                B: next_state = in ? B:A;
            endcase

            // State flip-flops
            present_state = next_state;   

            case (present_state)
                // Fill in output logic
                A: out = 0;
                B: out = 1;
            endcase
        end
    end

endmodule

一开始输出一直不匹配，才发现在复位判断内没有给输出out赋值。这算是三段式和一段式的一个注意事项吧。

3.Simple FSM2

题目：

This is a Moore state machine with two states, two inputs, and one output. Implement this state machine.

This exercise is the same as fsm2s, but using asynchronous reset.

思路：

题目给出了一个JK触发器，包含2个输入J、K，一个输出out，异步复位，代码为三段式。与题1思路类似。

代码：

module top_module(
    input cl