HDLBits: 有限状态机

原创

已于 2025-09-21 11:49:17 修改 · 352 阅读

0 ·

CC 4.0 BY-SA版权

文章标签：

#fpga开发

于 2025-09-19 10:09:03 首次发布

简单 FSM: 同步复位

// Note the Verilog-1995 module declaration syntax here:
module top_module(clk, reset, in, out);
    input clk;
    input reset;    // Synchronous reset to state B
    input in;
    output out;//  
    reg out;

    // Fill in state name declarations
    parameter A = 1'b0, B = 1'b1;  

    reg present_state, next_state;

    always @(posedge clk) begin
        if (reset) begin  
            // Fill in reset logic
            present_state <= B;
        end
        else begin
        	present_state <= next_state;
        end
    end
    
    // 组合的状态转移逻辑
    always @(*) begin
        case (present_state)
        	A : next_state <= in == 0 ? B : A;
            B : next_state <= in == 0 ? A : B;
        endcase
        
        out = present_state;
    end
    
    

endmodule