详细分析“/* 1.14.0 */
/*===================================================================================================================================*/
/* Copyright DENSO Corporation */
/*===================================================================================================================================*/
/* Spansion Traveo ARM Cortex-FR5/R5F : statup_acr5f.asm */
/* */
/* Compiler : Greenhills ARM */
/* */
/* Usage of General Register : */
/* R0 : */
/* R1 : */
/* R2 : Copy, Fill Buffer for M_COPY, M_FILLZ */
/* R3 : Copy, Fill Buffer for M_COPY, M_FILLZ */
/* R4 : Copy, Fill Buffer for M_COPY, M_FILLZ */
/* R5 : Copy, Fill Buffer for M_COPY, M_FILLZ */
/* R6 : Copy, Fill Buffer for M_COPY, M_FILLZ */
/* R7 : Copy, Fill Buffer for M_COPY, M_FILLZ */
/* R8 : Copy, Fill Buffer for M_COPY, M_FILLZ */
/* R9 : Copy, Fill Buffer for M_COPY, M_FILLZ */
/* R10 : Auto variables for M_COPY, M_FILLZ */
/* R11 : Auto variables for M_COPY, M_FILLZ */
/* R12 : Auto variables for M_COPY, M_FILLZ */
/* R13 : = sp Stack Pointer */
/* R14 : = lr Link Register, Auto variables for M_COPY */
/* R15 : = pc Program Counter */
/*===================================================================================================================================*/
/*-----------------------------------------------------------------------------------------------------------------------------------*/
/* Version */
/*-----------------------------------------------------------------------------------------------------------------------------------*/
#define STARTUP_ASM_MAJOR (1)
#define STARTUP_ASM_MINOR (14)
#define STARTUP_ASM_PATCH (0)
/*-----------------------------------------------------------------------------------------------------------------------------------*/
/* Include File */
/*-----------------------------------------------------------------------------------------------------------------------------------*/
#include "startup_acr5f_asmopt.h"
/*-----------------------------------------------------------------------------------------------------------------------------------*/
/* Version Check */
/*-----------------------------------------------------------------------------------------------------------------------------------*/
#if ((STARTUP_ASM_MAJOR != STARTUP_ASM_OPT_H_MAJOR) ||\
(STARTUP_ASM_MINOR != STARTUP_ASM_OPT_H_MINOR) ||\
(STARTUP_ASM_PATCH != STARTUP_ASM_OPT_H_PATCH))
#error "startup_acr5f.arm and startup_acr5f_asmopt.h : source and parameter files are inconsistent!"
#endif
/*-----------------------------------------------------------------------------------------------------------------------------------*/
/* external declaration of symbols */
/*-----------------------------------------------------------------------------------------------------------------------------------*/
.export _start
.export vd_g_StartupJumpRstvct
.export vd_g_StartupMemFillz
.import vd_g_StartupMpuInit
.import vd_g_StartupPpuInit
.import vd_g_StartupTcmInit
.import vd_g_StartupFblEntryClearMark
#if (defined(__STARTUP_XMPU_INIT_ENA__) && (__STARTUP_XMPU_INIT_ENA__== 1))
.import vd_g_StartupXMpuInit
#endif
#if (defined(__STARTUP_JTAG_INIT_ENA__) && (__STARTUP_JTAG_INIT_ENA__== 1))
.import vd_g_StartupJTAGInit
#endif
#if (defined(__STARTUP_INT_HNDLR_ENA__) && (__STARTUP_INT_HNDLR_ENA__ == 1))
.import vd_STARTUP_EXC_INIT
.import vd_STARTUP_FIQ_INIT
#endif
.import u4_g_STARTUP_TCFLSH_ECC_INIT
.import st_gp_STARTUP_SC_CPINI
.import u1_g_STARTUP_NUM_SC_CPINI
.import st_gp_STARTUP_SC_FILLZ
.import u1_g_STARTUP_NUM_SC_FILLZ
.import u4_g_STARTUP_BRI_BY_MCU_RST
.import u4_g_STARTUP_BRI_BY_PDX_RST
.import st_gp_STARTUP_SC_BRAM
.import u1_g_STARTUP_NUM_SC_BRAM
.import u4p_gp_STARTUP_STACK_INIT
.import fp_g_vd_STARTUP_PRGM_MAIN
.import u1_g_STARTUP_JMP_RV_NMI_CH
/*-----------------------------------------------------------------------------------------------------------------------------------*/
/* local definitions */
/*-----------------------------------------------------------------------------------------------------------------------------------*/
STARTUP_CPSR_MBIT_FIELDS EQU 0x1F
STARTUP_CPSR_MBIT_USR EQU 0x10
STARTUP_CPSR_MBIT_FIQ EQU 0x11
STARTUP_CPSR_MBIT_IRQ EQU 0x12
STARTUP_CPSR_MBIT_SVC EQU 0x13
STARTUP_CPSR_MBIT_ABT EQU 0x17
STARTUP_CPSR_MBIT_UND EQU 0x1B
STARTUP_CPSR_MBIT_SYS EQU 0x1F /* shares stack with USR mode */
STARTUP_CPSR_FIRQ_DIS EQU 0x40
/*-----------------------------------------------------------------------------------------------------------------------------------*/
STARTUP_ARM_SYSCTRL_INIT EQU 0x09ed287a /* Refer manuals/Platform/MCAL/Spa_Traveo/Startup_ARM_core_configuration.xlsx */
STARTUP_ARM_AUX_LO_INIT EQU 0x0021 /* Refer manuals/Platform/MCAL/Spa_Traveo/Startup_ARM_core_configuration.xlsx */
STARTUP_ARM_AUX_HI_ATCM_ECC_EN EQU 0x0e00 /* Refer manuals/Platform/MCAL/Spa_Traveo/Startup_ARM_core_configuration.xlsx */
STARTUP_ARM_AUX_HI_ATCM_ECC_DI EQU 0x0c00 /* Refer manuals/Platform/MCAL/Spa_Traveo/Startup_ARM_core_configuration.xlsx */
STARTUP_ARM_SAUXCTRL_INIT EQU 0x00400004 /* Refer manuals/Platform/MCAL/Spa_Traveo/Startup_ARM_core_configuration.xlsx */
/*-----------------------------------------------------------------------------------------------------------------------------------*/
STARTUP_RADDR_MCU_RST EQU 0xb0600390
STARTUP_RADDR_PDX_RST EQU 0xb0600398
/*-----------------------------------------------------------------------------------------------------------------------------------*/
STARTUP_RADDR_IRC_UNLOCK EQU 0xb0400d30 /* IRC0_UNLOCK */
STARTUP_RADDR_IRC_NMI_VCT EQU 0xb0400010 /* IRC0_NMIVA0 */
STARTUP_RADDR_IRC_NMI_RQS EQU 0xb0400ab0 /* IRC0_NMIS */
STARTUP_RADDR_IRC_NMI_PLV EQU 0xb0400890 /* IRC0_PL0 */
STARTUP_RADDR_IRC_NMI_HC EQU 0xb0400c40 /* IRC0_NMIHC */
STARTUP_IRC_KEY_RELS EQU 0x17acc911
STARTUP_IRC_KEY_LOCK EQU 0x17b10c11
/*-----------------------------------------------------------------------------------------------------------------------------------*/
/* Section Definition */
/*-----------------------------------------------------------------------------------------------------------------------------------*/
.section ".text_APPL_START", "ax"
.nothumb /* Instruction Mode = ARM */
/*-----------------------------------------------------------------------------------------------------------------------------------*/
/* Macro */
/*-----------------------------------------------------------------------------------------------------------------------------------*/
/*===================================================================================================================================*/
/* M_COPY */
/* --------------------------------------------------------------------------------------------------------------------------------- */
/* Arguments: - */
/* Return: - */
/*===================================================================================================================================*/
.macro M_COPY cfg
.macrolocal mcopy32b_next, mcopy8b_init, mcopy8b_next, mcopy8b_end, mcopy_end
LDR r10, [cfg] /* Start address ROM Area */
LDR r11, [cfg, #4] /* End address ROM Area */
LDR r12, [cfg, #8] /* Start address RAM Area */
CMP r10, r11
BHS mcopy_end /* Start Address >= End Address */
SUB r14, r11, r10
CMP r14, #32
BLO mcopy8b_init /* size < 32 byte */
mcopy32b_next:
LDM r10!, {r2-r9} /* copy 32 bytes */
STM r12!, {r2-r9}
SUB r14, r14, #32
CMP r14, #32
BHS mcopy32b_next
mcopy8b_init:
CMP r14, #8
BLO mcopy8b_end
mcopy8b_next:
LDM r10!, {r2,r3} /* copy 8 bytes */
STM r12!, {r2,r3}
SUB r14, r14, #8
CMP r14, #8
BHS mcopy8b_next
mcopy8b_end:
CMP r14, #0
BEQ mcopy_end
LDM r10!, {r2,r3} /* copy 8 bytes */
STM r12!, {r2,r3}
mcopy_end:
.endm
/*===================================================================================================================================*/
/* M_FILLZ */
/* --------------------------------------------------------------------------------------------------------------------------------- */
/* Arguments: - */
/* Return: - */
/*===================================================================================================================================*/
.macro M_FILLZ cfg
.macrolocal mfillz32b_next, mfillz8b_init, mfillz8b_next, mfillz8b_end, mfillz_end
LDR r10, [cfg] /* Start address RAM Area */
LDR r11, [cfg, #4] /* End address RAM Area */
CMP r10, r11
BHS mfillz_end /* Start Address >= End Address */
SUB r12, r11, r10
CMP r12, #32
BLO mfillz8b_init
mfillz32b_next:
STM r10!, {r2-r9} /* write 32 bytes */
SUB r12, r12, #32
CMP r12, #32
BHS mfillz32b_next
mfillz8b_init:
CMP r12, #8
BLO mfillz8b_end
mfillz8b_next:
STM r10!, {r2,r3} /* write 8 bytes */
SUB r12, r12, #8
CMP r12, #8
BHS mfillz8b_next
mfillz8b_end:
CMP r12, #0
BEQ mfillz_end
STM r10!, {r2,r3} /* write 8 bytes */
mfillz_end:
.endm
/*-----------------------------------------------------------------------------------------------------------------------------------*/
/* Variable Definitions */
/*-----------------------------------------------------------------------------------------------------------------------------------*/
/*-----------------------------------------------------------------------------------------------------------------------------------*/
/* Constant Variable Definitions */
/*-----------------------------------------------------------------------------------------------------------------------------------*/
/*-----------------------------------------------------------------------------------------------------------------------------------*/
/* Static Function Prototypes */
/*-----------------------------------------------------------------------------------------------------------------------------------*/
/*-----------------------------------------------------------------------------------------------------------------------------------*/
/* Function Definitions */
/*-----------------------------------------------------------------------------------------------------------------------------------*/
/*===================================================================================================================================*/
/* void _start(void) */
/* --------------------------------------------------------------------------------------------------------------------------------- */
/* Arguments: - */
/* Return: - */
/*===================================================================================================================================*/
_start:
CPSID AI /* disable asynchronous aborts(clear A bit) */
/* disable IRQ */
/* ------------------------------------------------- */
/* disable MPU in ARM Core and i/d-Cache */
/* ------------------------------------------------- */
MOVW r0, #(STARTUP_ARM_SYSCTRL_INIT & 0xffff)
MOVT r0, #(STARTUP_ARM_SYSCTRL_INIT >> 16 )
DSB
MCR p15, 0, r0, c1, c0, 0
ISB /* Instruction Synchronization Barrier */
/* ------------------------------------------------- */
/* TCRAM/TCFlash ECC Configuration */
/* ------------------------------------------------- */
MOVW r0, #(STARTUP_ARM_AUX_LO_INIT)
MOVW r1, %lo(u4_g_STARTUP_TCFLSH_ECC_INIT)
MOVT r1, %hi(u4_g_STARTUP_TCFLSH_ECC_INIT)
LDR r1, [r1]
MOVW r2, #(STARTUP_TCFLSH_ECC_EN & 0xffff)
MOVT r2, #(STARTUP_TCFLSH_ECC_EN >> 16 )
CMP r1, r2
MOVTNE r0, #(STARTUP_ARM_AUX_HI_ATCM_ECC_DI)
MOVTEQ r0, #(STARTUP_ARM_AUX_HI_ATCM_ECC_EN)
DSB
MCR p15, 0, r0, c1, c0, 1
DSB
MOVW r0, #(STARTUP_ARM_SAUXCTRL_INIT & 0xffff)
MOVT r0, #(STARTUP_ARM_SAUXCTRL_INIT >> 16 )
DSB
MCR p15, 0, r0, c15, c0, 0 /* ATCMECC Correction for internal ECC logic is disabled */
/* Since TCM Port A is connect to TCFLASH, write back operation */
/* by 1 bit error correction could cause redundant bus-error, i.g */
/* Prefech/Data Abort. In order to avoid the error, 1 bit error */
/* correction is disabled. */
DSB
/* ------------------------------------------------- */
/* ARM MPU Initialization */
/* ------------------------------------------------- */
MOVW r12, %lo(vd_g_StartupMpuInit)
MOVT r12, %hi(vd_g_StartupMpuInit)
BLX r12
/* ------------------------------------------------- */
/* Traveo Peripheral Protection Initialization */
/* ------------------------------------------------- */
MOVW r12, %lo(vd_g_StartupPpuInit)
MOVT r12, %hi(vd_g_StartupPpuInit)
BLX r12
/* ------------------------------------------------- */
/* Traveo TC RAM/ROM IF Initialization */
/* ------------------------------------------------- */
MOVW r12, %lo(vd_g_StartupTcmInit)
MOVT r12, %hi(vd_g_StartupTcmInit)
BLX r12
/* ------------------------------------------------- */
/* ".data" Section Initialization */
/* ------------------------------------------------- */
MOVW r0, %lo(u1_g_STARTUP_NUM_SC_CPINI)
MOVT r0, %hi(u1_g_STARTUP_NUM_SC_CPINI)
LDRB r0, [r0]
CMP r0, #0
BEQ startup_bss_init
MOVW r1, %lo(st_gp_STARTUP_SC_CPINI)
MOVT r1, %hi(st_gp_STARTUP_SC_CPINI)
startup_data_init_next:
M_COPY r1
ADD r1, r1, #12
SUB r0, r0, #1
CMP r0, #0
BNE startup_data_init_next
/* ------------------------------------------------- */
/* ".bss" Section Initialization */
/* ------------------------------------------------- */
startup_bss_init:
MOV r2, #0
MOV r3, #0
MOV r4, #0
MOV r5, #0
MOV r6, #0
MOV r7, #0
MOV r8, #0
MOV r9, #0
MOVW r0, %lo(u1_g_STARTUP_NUM_SC_FILLZ)
MOVT r0, %hi(u1_g_STARTUP_NUM_SC_FILLZ)
LDRB r0, [r0]
CMP r0, #0
BEQ startup_bram_init
MOVW r1, %lo(st_gp_STARTUP_SC_FILLZ)
MOVT r1, %hi(st_gp_STARTUP_SC_FILLZ)
startup_bss_init_next:
M_FILLZ r1
ADD r1, r1, #8
SUB r0, r0, #1
CMP r0, #0
BNE startup_bss_init_next
/* ------------------------------------------------- */
/* .bss_BACK_XXX Initialization */
/* ------------------------------------------------- */
startup_bram_init:
MOVW r0, %lo(u4_g_STARTUP_BRI_BY_MCU_RST)
MOVT r0, %hi(u4_g_STARTUP_BRI_BY_MCU_RST)
LDR r0, [r0]
MOVW r1, #(STARTUP_RADDR_MCU_RST & 0xffff)
MOVT r1, #(STARTUP_RADDR_MCU_RST >> 16 )
LDR r1, [r1] /* Load Register Value */
AND r1, r0, r1
CMP r1, #0
BNE startup_bram_init_2nd
MOVW r0, %lo(u4_g_STARTUP_BRI_BY_PDX_RST)
MOVT r0, %hi(u4_g_STARTUP_BRI_BY_PDX_RST)
LDR r0, [r0]
MOVW r1, #(STARTUP_RADDR_PDX_RST & 0xffff)
MOVT r1, #(STARTUP_RADDR_PDX_RST >> 16 )
LDR r1, [r1] /* Load Register Value */
AND r1, r0, r1
CMP r1, #0
BEQ startup_stack_init
startup_bram_init_2nd:
MOVW r0, %lo(u1_g_STARTUP_NUM_SC_BRAM)
MOVT r0, %hi(u1_g_STARTUP_NUM_SC_BRAM)
LDRB r0, [r0]
CMP r0, #0
BEQ startup_stack_init
MOVW r1, %lo(st_gp_STARTUP_SC_BRAM)
MOVT r1, %hi(st_gp_STARTUP_SC_BRAM)
startup_bram_init_next:
M_FILLZ r1
ADD r1, r1, #8
SUB r0, r0, #1
CMP r0, #0
BNE startup_bram_init_next
/* ------------------------------------------------- */
/* Stack Pointer Initialization */
/* ------------------------------------------------- */
startup_stack_init:
MOVW r1, %lo(u4p_gp_STARTUP_STACK_INIT)
MOVT r1, %hi(u4p_gp_STARTUP_STACK_INIT)
CPS #STARTUP_CPSR_MBIT_FIQ
LDR sp, [r1, #STARTUP_STACK_INIT_FIQ] /* Top of FIQ stack */
CPS #STARTUP_CPSR_MBIT_IRQ
LDR sp, [r1, #STARTUP_STACK_INIT_IRQ] /* Top of IRQ stack */
CPS #STARTUP_CPSR_MBIT_ABT
LDR sp, [r1, #STARTUP_STACK_INIT_ABT] /* Top of ABT stack */
CPS #STARTUP_CPSR_MBIT_UND
LDR sp, [r1, #STARTUP_STACK_INIT_UND] /* Top of UND stack */
CPS #STARTUP_CPSR_MBIT_SVC
LDR sp, [r1, #STARTUP_STACK_INIT_SVC] /* Top of SVC stack */
CPS #STARTUP_CPSR_MBIT_SYS
LDR sp, [r1, #STARTUP_STACK_INIT_SYS] /* Top of SYS stack */
#if (defined(__STARTUP_XMPU_INIT_ENA__) && (__STARTUP_XMPU_INIT_ENA__== 1))
MOVW r12, %lo(vd_g_StartupXMpuInit)
MOVT r12, %hi(vd_g_StartupXMpuInit)
BLX r12
#endif /* #if (defined(__STARTUP_XMPU_INIT_ENA__) && (__STARTUP_XMPU_INIT_ENA__== 1)) */
#if (defined(__STARTUP_JTAG_INIT_ENA__) && (__STARTUP_JTAG_INIT_ENA__== 1))
MOVW r12, %lo(vd_g_StartupJTAGInit)
MOVT r12, %hi(vd_g_StartupJTAGInit)
BLX r12
#endif /* #if (defined(__STARTUP_JTAG_INIT_ENA__) && (__STARTUP_JTAG_INIT_ENA__== 1)) */
#if (defined(__STARTUP_INT_HNDLR_ENA__) && (__STARTUP_INT_HNDLR_ENA__ == 1))
MOVW r12, %lo(vd_STARTUP_EXC_INIT)
MOVT r12, %hi(vd_STARTUP_EXC_INIT)
BLX r12
CPSIE A /* enable asynchronous aborts(clear A bit) */
MOVW r12, %lo(vd_STARTUP_FIQ_INIT)
MOVT r12, %hi(vd_STARTUP_FIQ_INIT)
BLX r12
CPSIE F /* enable FIQ(clear F bit) */
#endif /* #if (defined(__STARTUP_INT_HNDLR_ENA__) && (__STARTUP_INT_HNDLR_ENA__ == 1)) */
MOVW r12, %lo(vd_g_StartupFblEntryClearMark)
MOVT r12, %hi(vd_g_StartupFblEntryClearMark)
BLX r12
/* execute main function */
MOVW r12, %lo(fp_g_vd_STARTUP_PRGM_MAIN)
MOVT r12, %hi(fp_g_vd_STARTUP_PRGM_MAIN)
LDR r12, [r12]
BX r12
/* Reset MCU */
_start_end:
B _start_end
/*===================================================================================================================================*/
/* void vd_g_StartupJumpRstvct(void) */
/* --------------------------------------------------------------------------------------------------------------------------------- */
/* Arguments: - */
/* Return: - */
/*===================================================================================================================================*/
vd_g_StartupJumpRstvct:
MRS r0, cpsr /* Original CPSR value */
AND r1, r0, #STARTUP_CPSR_MBIT_FIELDS
CMP r1, #STARTUP_CPSR_MBIT_USR
BEQ startup_jump_rstvct_ret
AND r1, r0, #STARTUP_CPSR_FIRQ_DIS
CMP r1, #0 /* CPSR.F = 0 */
BNE _start /* IF CPRS.F = 1, jump _start */
MOVW r0, #(STARTUP_RADDR_IRC_UNLOCK & 0xffff)
MOVT r0, #(STARTUP_RADDR_IRC_UNLOCK >> 16 )
MOVW r1, #(STARTUP_IRC_KEY_RELS & 0xffff)
MOVT r1, #(STARTUP_IRC_KEY_RELS >> 16 )
STR r1, [r0]
MOVW r1, %lo(u1_g_STARTUP_JMP_RV_NMI_CH)
MOVT r1, %hi(u1_g_STARTUP_JMP_RV_NMI_CH)
LDRB r1, [r1]
MOVW r2, #(STARTUP_RADDR_IRC_NMI_VCT & 0xffff)
MOVT r2, #(STARTUP_RADDR_IRC_NMI_VCT >> 16 )
ADD r2, r2, r1, LSL #2 /* IRC0_NMIVA0 + NMI CH * 4byte */
MOVW r3, %lo(vd_s_StartupJumpRstvctNMI)
MOVT r3, %hi(vd_s_StartupJumpRstvctNMI)
STR r3, [r2]
CMP r1, #0
BEQ startup_jump_rstvct_nmi_call
MOVW r2, #(STARTUP_RADDR_IRC_NMI_PLV & 0xffff)
MOVT r2, #(STARTUP_RADDR_IRC_NMI_PLV >> 16 )
ADD r2, r1, r2
MOV r3, #0
STRB r3, [r2]
startup_jump_rstvct_nmi_call:
MOVW r2, #(STARTUP_RADDR_IRC_NMI_RQS & 0xffff)
MOVT r2, #(STARTUP_RADDR_IRC_NMI_RQS >> 16 )
MOV r3, #0x01
LSL r3, r1
STR r3, [r2] /* Set Software NMI Request */
DMB
CPSIE F /* enable FIQ(clear F bit) */
B _start_end /* Failsafe */
startup_jump_rstvct_ret
BX lr
/*===================================================================================================================================*/
/* static void vd_s_StartupJumpRstvctNMI(void) */
/* --------------------------------------------------------------------------------------------------------------------------------- */
/* Arguments: - */
/* Return: - */
/*===================================================================================================================================*/
vd_s_StartupJumpRstvctNMI:
ADD r2, r2, #4 /* IRC0_NMIR */
STR r3, [r2] /* Clear Software NMI Request */
DMB
MOVW r2, #(STARTUP_RADDR_IRC_NMI_HC & 0xffff)
MOVT r2, #(STARTUP_RADDR_IRC_NMI_HC >> 16 )
STR r1, [r2]
MOVW r1, #(STARTUP_IRC_KEY_LOCK & 0xffff)
MOVT r1, #(STARTUP_IRC_KEY_LOCK >> 16 )
STR r1, [r0]
B _start
/*===================================================================================================================================*/
/* void vd_g_StartupMemFillz(const ST_STARTUP_FILLZ * st_ap_FILLZ) */
/* --------------------------------------------------------------------------------------------------------------------------------- */
/* Arguments: - */
/* Return: - */
/*===================================================================================================================================*/
vd_g_StartupMemFillz:
PUSH {r4-r12} /* Save argument register on system stack */
MOV r2, #0
MOV r3, #0
MOV r4, #0
MOV r5, #0
MOV r6, #0
MOV r7, #0
MOV r8, #0
MOV r9, #0
M_FILLZ r0
POP {r4-r12} /* Save argument register on system stack */
BX lr
/*===================================================================================================================================*/
/* file end */
/*===================================================================================================================================*/
END
/*===================================================================================================================================*/
/* */
/* Change History */
/* */
/*===================================================================================================================================*/
/* */
/* Version Date Author Change Description */
/* --------------- ---------- ------ ------------------------------------------------------------------------------------------- */
/* 1.0.0 06/26/2014 KT new */
/* 1.1.0 2/18/2015 TN Stack Pointers were changed to const from #define. */
/* 1.2.0 3/ 5/2015 TN vd_g_StartupRamFillz was implemented and the usage of general registerStack was optimized. */
/* 1.3.0 6/12/2015 TN M_FILLZ was modified. */
/* 1.4.0 9/ 7/2015 TN Initialization Sequence was optimized considering Flash Bootloader. */
/* 1.5.0 10/19/2015 TN Bug Fix : In M_FILLZ, RAM was not initialized if the size was less than 8 bytes. */
/* 1.6.0 10/23/2015 TN Improvement : STARTUP_CP15_INIT_MASK and STARTUP_CP15_INIT_SETBIT */
/* ->STARTUP_ARM_SYSCTRL_INIT_CLR and STARTUP_ARM_SYSCTRL_INIT_SET */
/* 1.7.0 11/13/2015 TN Improvement : u4_gp_STARTUP_MCU_RST_REASON and u4_gp_STARTUP_PDX_RST were replaced to macro. */
/* vd_g_StartupFblClrEntryMark was integrated. */
/* 1.8.0 12/ 2/2015 TN Improvement : ECC configuration for TCRAM/TCFLASH was implemented considering it of Flash */
/* Bootloader. */
/* 1.9.0 12/ 3/2015 TN Improvement : ARM Core Configuration was optimized. */
/* 1.10.0 12/18/2015 TN Improvement : vd_g_StartupMcuStart -> vd_g_StartupJumpRstvct. */
/* 1.11.0 2/25/2016 TN QAC warnings wer fixed. */
/* ST_STARTUP_FILLZ was defined in startup.h. */
/* startup_acr5f_cfg_private.h -> startup_acr5f_asmopt.h. */
/* 1.12.0 3/29/2016 TN #if ((defined(__AIP_DEBUG_SIM__)) && (__AIP_DEBUG_SIM__==1)) was deleted because Greenhills */
/* ARM simulator was updated and the bug was fixed. */
/* 1.13.0 6/ 6/2016 TN Improvement : u4_gp_STARTUP_STACK_INIT -> u4p_gp_STARTUP_STACK_INIT. */
/* 1.14.0 9/28/2016 TN u4_g_STARTUP_TCFLSH_ECC_INIT was created in order to make ATCM ECC configurable. */
/* */
/* * KT = Kensuke Tanaka, Denso Create */
/* * TN = Takashi Nagai, Denso */
/* */
/*===================================================================================================================================*/
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