fifo_top.sv

module fifo_top #(parameter DSIZE =8 ,parameter ADDRSIZE=4) (fifoPorts.DUT itf);
    fifo1  #(.DSIZE(DSIZE),.ASIZE(ADDRSIZE)) i0(
             .rdata(itf.rdata),
             .wfull(itf.wfull),
             .rempty(itf.rempty),
             .wdata(itf.wdata),
             .winc(itf.winc),
             .wclk(itf.wclk),
             .wrst_n(itf.wrst_n),
             .rinc(itf.rinc),
             .rclk(itf.rclk),
             .rrst_n(itf.rrst_n)
    );

    logic full_pre,empty_pre;

    always_comb begin
        full_pre=i0.i0.wptr_full.wfull_val;
        empty_pre =i0.i0.rptr_empty.rempty_val;
        itf.full_pre=full_pre;
        itf.empty_pre=empty_pre;
    end
//声明两个逻辑型变量full_pre和empty_pre,并在组合逻辑区块中将他们与fifo1模块的wptr_full
//和rptr_empty信号相连，并将它们的值赋给itf对应的接口full_pre和empty_pre
    property full_wr;
        @(posedge itf.wclk) !(itf.winc  && itf.wfull);
    endproperty
    check_full_write:assert property(full_wr)
                     else $fatal ("Error:fifo full_write occurred!");
//定义一个名为full_wr的属性，并使用时序逻辑@(posedge itf.wclk)来描述它的行为，这
//属性表示当写指针增加时，fifo未满
    property empty_rd;
        @(posedge itf.rclk) ! (itf.rinc && itf.rempty);
    endproperty
    check_rempty_read:assert property (empty_rd)a
                    else $fatal("Error:fifo empty read occured!");
endmodule