<?xml version="1.0" encoding="utf-8" ?><rss version="2.0"><channel><title><![CDATA[Analog4Fun的博客]]></title><description><![CDATA[]]></description><link>https://blog.youkuaiyun.com/Analog4Fun</link><language>zh-cn</language><generator>https://blog.youkuaiyun.com/</generator><copyright><![CDATA[Copyright &copy; Analog4Fun]]></copyright><item><title><![CDATA[Examples of The Fourier Series]]></title><link>https://blog.youkuaiyun.com/Analog4Fun/article/details/138513705</link><guid>https://blog.youkuaiyun.com/Analog4Fun/article/details/138513705</guid><author>Analog4Fun</author><pubDate>Tue, 07 May 2024 00:44:27 +0800</pubDate><description><![CDATA[典型傅立叶变换事例。]]></description><category></category></item><item><title><![CDATA[3 Packages Comparison: LFC, CSP and QFN]]></title><link>https://blog.youkuaiyun.com/Analog4Fun/article/details/137361152</link><guid>https://blog.youkuaiyun.com/Analog4Fun/article/details/137361152</guid><author>Analog4Fun</author><pubDate>Thu, 04 Apr 2024 00:17:46 +0800</pubDate><description><![CDATA[LFC (Low Profile Fine-pitch Chip Carrier), CSP (Chip Scale Package), and QFN (Quad Flat No-leads) are all types of integrated circuit packaging technologies, each with its own characteristics and applications. Here are the key differences between them:LFC ]]></description><category></category></item><item><title><![CDATA[Slew Rate]]></title><link>https://blog.youkuaiyun.com/Analog4Fun/article/details/136858603</link><guid>https://blog.youkuaiyun.com/Analog4Fun/article/details/136858603</guid><author>Analog4Fun</author><pubDate>Tue, 19 Mar 2024 23:40:48 +0800</pubDate><description><![CDATA[linear。]]></description><category></category></item><item><title><![CDATA[Dependent source model (VCVS, CCCS, CCVS, VCCS)]]></title><link>https://blog.youkuaiyun.com/Analog4Fun/article/details/135762082</link><guid>https://blog.youkuaiyun.com/Analog4Fun/article/details/135762082</guid><author>Analog4Fun</author><pubDate>Tue, 23 Jan 2024 06:00:49 +0800</pubDate><description><![CDATA[]]></description><category></category></item><item><title><![CDATA[Review of CMRR]]></title><link>https://blog.youkuaiyun.com/Analog4Fun/article/details/135664105</link><guid>https://blog.youkuaiyun.com/Analog4Fun/article/details/135664105</guid><author>Analog4Fun</author><pubDate>Thu, 18 Jan 2024 05:45:58 +0800</pubDate><description><![CDATA[Input CM variations disturb the bias pionts, alternating the small-signal gain and possibly limiting the output voltage swings. More troublesome is the variation of the diff output as a result of a change in Vin,cm, since the circuit is not fully symmetric]]></description><category></category></item><item><title><![CDATA[Sampling Theorem]]></title><link>https://blog.youkuaiyun.com/Analog4Fun/article/details/126047470</link><guid>https://blog.youkuaiyun.com/Analog4Fun/article/details/126047470</guid><author>Analog4Fun</author><pubDate>Sun, 07 Aug 2022 13:23:38 +0800</pubDate><description><![CDATA[Sampling Theorem]]></description><category></category></item><item><title><![CDATA[Summary of Feedback System]]></title><link>https://blog.youkuaiyun.com/Analog4Fun/article/details/125551316</link><guid>https://blog.youkuaiyun.com/Analog4Fun/article/details/125551316</guid><author>Analog4Fun</author><pubDate>Fri, 01 Jul 2022 05:20:57 +0800</pubDate><description><![CDATA[Summary of Feedback System]]></description><category></category></item><item><title><![CDATA[Chopper Amplifier]]></title><link>https://blog.youkuaiyun.com/Analog4Fun/article/details/125345514</link><guid>https://blog.youkuaiyun.com/Analog4Fun/article/details/125345514</guid><author>Analog4Fun</author><pubDate>Sat, 18 Jun 2022 12:19:16 +0800</pubDate><description><![CDATA[chopper amplifier]]></description><category></category></item><item><title><![CDATA[拉氏变换应用]]></title><link>https://blog.youkuaiyun.com/Analog4Fun/article/details/124701773</link><guid>https://blog.youkuaiyun.com/Analog4Fun/article/details/124701773</guid><author>Analog4Fun</author><pubDate>Wed, 11 May 2022 05:48:41 +0800</pubDate><description><![CDATA[由系统函数零、极点分别决定时域特性

（一）零、极点分布与波形特征的对应
的零、极点：
典型情况极点分布与原函数波形对应关系

极点位于s平面坐标原点，冲激响应为阶跃函数
	极点位于s平面实轴上，冲激响应具有指数形式，正为指数增长，负为指数衰减
	虚轴上共轭极点给出等幅振荡
	极点落在s平面左平面内共轭极点对应衰减震荡（左平面衰减，共轭极点振荡）
多重极点典型情况（一般几重极点就乘上t的几次方）

位于s平面坐标原点的二阶或三阶极点分别给出时间函数为t或他(1/2)t^2
	实轴上二阶极点给出t与指数函数的]]></description><category></category></item><item><title><![CDATA[PSS and PNoise]]></title><link>https://blog.youkuaiyun.com/Analog4Fun/article/details/124358089</link><guid>https://blog.youkuaiyun.com/Analog4Fun/article/details/124358089</guid><author>Analog4Fun</author><pubDate>Sun, 24 Apr 2022 12:01:30 +0800</pubDate><description><![CDATA[1. PSS: periodic steady-state

Using Harmonic balance (in the frequency domain): 1)simulating weak non-linear circuits; 2) handling frequency dependent components

or shooting (in the time domain): highly non-linear circuits with sharply rising and falling]]></description><category></category></item><item><title><![CDATA[Jitter]]></title><link>https://blog.youkuaiyun.com/Analog4Fun/article/details/124286183</link><guid>https://blog.youkuaiyun.com/Analog4Fun/article/details/124286183</guid><author>Analog4Fun</author><pubDate>Wed, 20 Apr 2022 01:15:03 +0800</pubDate><description><![CDATA[1. Period Jitter

file:///Users/ssong/Downloads/AN10007-Jitter-and-measurement%20(3).pdf

1.1 Period jitter is the deviation in cycle time of a clock signal with respect to the ideal period over a number of randomly selected cycles.Period jitter is...]]></description><category></category></item><item><title><![CDATA[Convolution]]></title><link>https://blog.youkuaiyun.com/Analog4Fun/article/details/124139027</link><guid>https://blog.youkuaiyun.com/Analog4Fun/article/details/124139027</guid><author>Analog4Fun</author><pubDate>Wed, 13 Apr 2022 05:13:37 +0800</pubDate><description><![CDATA[概率论中，两个统计独立变量X与Y的和的概率密度函数(PDF) 是X与Y的概率密度函数的卷积。

如何通俗易懂地解释卷积？ - 知乎

卷积，这个堪称神解释 - 知乎
]]></description><category></category></item><item><title><![CDATA[Power consumption (Low power design)]]></title><link>https://blog.youkuaiyun.com/Analog4Fun/article/details/123027035</link><guid>https://blog.youkuaiyun.com/Analog4Fun/article/details/123027035</guid><author>Analog4Fun</author><pubDate>Sun, 20 Feb 2022 23:50:22 +0800</pubDate><description><![CDATA[https://www.eurasip.org/Seminars/EURASIPLowPowerSeminar_talk1.pdf






































]]></description><category></category></item><item><title><![CDATA[Dennard scaling]]></title><link>https://blog.youkuaiyun.com/Analog4Fun/article/details/123026980</link><guid>https://blog.youkuaiyun.com/Analog4Fun/article/details/123026980</guid><author>Analog4Fun</author><pubDate>Sun, 20 Feb 2022 07:59:24 +0800</pubDate><description><![CDATA[Dennard提出，晶体管的尺寸在每一代技术中都缩小了30% (0.7倍)，因此它们的面积A减少了50%。这意味着电路减少了30% (0.7倍)的延迟，因此增加了约40% (1.4倍)的工作频率。最后，为了保持电场恒定，电压降低了30%，能量降低了65%，功率降低了50%。因此，在每一代技术中，晶体管密度增加一倍，电路速度提高40%，功耗(晶体管数量增加一倍)保持不变(https://www.ithome.com/0/451/930.htm)。

1 Dennard et al. Design of...]]></description><category></category></item><item><title><![CDATA[Resistor Tempco]]></title><link>https://blog.youkuaiyun.com/Analog4Fun/article/details/122872580</link><guid>https://blog.youkuaiyun.com/Analog4Fun/article/details/122872580</guid><author>Analog4Fun</author><pubDate>Fri, 11 Feb 2022 03:23:03 +0800</pubDate><description><![CDATA[TSMC

Ppoly (Neg tempco)

typ: 39.96K ohm

-40C: 41.04K ohm, +2.7%

125C: 38.84K ohm, -2.8%



Rmetal (Pos tempco)

typ: 5 ohm

-40C: 4.192 ohm, -16.16%

125C: 6.222 ohm, +24.44%


]]></description><category></category></item><item><title><![CDATA[Latch-up]]></title><link>https://blog.youkuaiyun.com/Analog4Fun/article/details/122486447</link><guid>https://blog.youkuaiyun.com/Analog4Fun/article/details/122486447</guid><author>Analog4Fun</author><pubDate>Fri, 14 Jan 2022 12:50:02 +0800</pubDate><description><![CDATA[Latch up 最易产生在易受外部干扰的I/O电路处, 也偶尔发生在内部电路。

1. 原理

Latch up 是指cmos晶片中, 在电源power VDD和地线GND(VSS)之间由于寄生的PNP和NPN双极性BJT相互影响而产生的一低阻抗通路, 它的存在会使VDD和GND之间产生大电流。

Latch-up发生的条件：

(i)当两个BJT都导通，在VDD和GND之间产生低阻抗通路;

(ii) 两个晶体管反馈回路（feedback loop）增益的乘积大于1;





PNP为一垂直式PNP ]]></description><category></category></item><item><title><![CDATA[RHP-Zero]]></title><link>https://blog.youkuaiyun.com/Analog4Fun/article/details/122273375</link><guid>https://blog.youkuaiyun.com/Analog4Fun/article/details/122273375</guid><author>Analog4Fun</author><pubDate>Sun, 02 Jan 2022 07:36:36 +0800</pubDate><description><![CDATA[https://www.powerelectronics.com/technologies/power-management/article/21860287/understanding-the-righthalfplane-zero-part-1

任何升压类变换器，工作于连续导电模式都会存在右半平面零点。减弱和消除右半平面零点的方式有很多，最简单的方式就是工作于DCM模式。

Boost变换器，右半平面零点直接体现为：负载发生变化时，占空比不会立即向稳态值靠近，因此瞬态响应性能较差，也导致了补偿网络较难]]></description><category></category></item><item><title><![CDATA[Pole location vs. Tran behavior]]></title><link>https://blog.youkuaiyun.com/Analog4Fun/article/details/122206272</link><guid>https://blog.youkuaiyun.com/Analog4Fun/article/details/122206272</guid><author>Analog4Fun</author><pubDate>Wed, 29 Dec 2021 01:58:06 +0800</pubDate><description><![CDATA[https://web.mit.edu/2.14/www/Handouts/PoleZero.pdf

The location of the poles in the s-plane therefore define the n components in the homogeneous response as described below:

1. A real pole pi = −σ in the left-half of the s-plane defines an exponentially ]]></description><category></category></item></channel></rss>