TCL: write_project_tcl description

REF

tclapp/xilinx/projutils/doc/write_project_tcl

Description:

Create a Tcl script to re-create the current project. The generated script will contain the Tcl commands for creating the project, setting the project type, creating filesets, adding/importing source files, and defining runs and run properties. The re-created project will be functionally equivalent to the original project.

This generated Tcl project script and the various design sources can be stored in a version control system for source file management and project archival.

To re-create the project, you should source the generated Tcl script in a Vivado Tcl shell from the same directory where the script was generated. If the original project already exists in the same project directory, the script may fail with an error message that the project already exists. In this case you may want to run the script from a different directory path or update the generated script by adding a “-force” switch to the “create_project” command.

In the generated Tcl script, the project source files are referenced relative to the “origin_dir” variable. By default, the source files are referenced relative to the directory where the tcl script is generated. The “origin_dir” is set to “.” (the current tcl script directory). When the script is executed from this directory, any source files will be referenced relative to this ‘origin_dir’ path value.

In the case where the script is sourced from a different directory or physically moved to a different directory, then the “origin_dir” variable MUST be manually set relative to the new directory. Manually set the “origin_dir” to make sure that the source files are correctly referenced relative to the original location.

You can have the “origin_dir” automatically set to a directory of your choice by using the -paths_relative_to option. All the source file paths will be defined relative to the directory specified with this option.

If -absolute_path is specified, the project source files will be referenced using absolute paths only. In this case, the script can be executed from any directory provided these absolute paths are accessible in the same filesystem.

If the original project contains IP cores, the following rules apply in the generated script while re-creating the project:-

  1. The IP will not be regenerated, if it was generated in the original project.
    
    In this case, the script will “add” the IP from the original project with generated synthesis/simulation products.

  2. The IP will be generated, if it was not generated in the original project.

In this case, the script will “add” the IP from the original project and create OOC synthesis runs for generating the synthesis/simulation products.

If the original project had completed runs, those runs will be re-created with the same settings in the generated project; however those runs will not be automatically launched in order to save runtime.

Arguments:

-paths_relative_to - (Optional) Specify the directory path relative to which the sources will referenced when re-creating the project. The path will be set for the “origin_dir” variable in the generated script.

-target_proj_dir - (Optional) Specify the directory path where the project will be recreated. The tool will write “create_project” command with the directory path specified with this switch.

-force - (Optional) Overwrite an existing project script file of the same name. If the script file already exists, the tool returns an error unless the -force argument is specified.

-all_properties - (Optional) Write all properties (default and non-default) for the project. The tool will write “set_property” commands for setting the properties for objects like project, filesets, files, runs etc.

Note: By default, if the -all_properties switch is not specified, then only the non-default properties will be written to the script.

-no_copy_sources - (Optional) Do not import sources even if they are local to the original project. The tool will not import the files that were local in the original project into the new project. If the design contains BD sources then -use_bd_files switch must also be provided.

-no_ip_version - (Optional) Flag to not include the IP version as part of the IP VLNV in create_bd_cell commands. NOTE - this may have implications if there are major IP version changes.

-absolute_path - (Optional) Make all file paths absolute in the generated script. This allows running the script from any location in that filesystem. By default the file paths will be relative to the origin_dir variable.

-dump_project_info - (Optional) Dump information about all properties to two text files, <project_name>_dump.txt (short), and <project_name>_def_val.txt (detailed).

-use_bd_files - (Optional) Use block design sources directly instead of writing out procs to create them. If the -no_copy_sources switch is provided the BD files will be added (but not copied locally) to the project. Otherwise the files will be imported (copied locally) to the project.

-internal - (Optional) Print only basic header information in the generated tcl script. By default information about required file sources will also be part of the header.

-quiet - (Optional) Execute the command quietly, returning only ERROR messages.

-verbose - (Optional) Temporarily override any message limits and return all messages from this command.

Note: Message limits can be defined with the set_msg_config command.

- (Required) The name of the output Tcl script file to be created by the write_project_tcl command. The tool will apply an extension of ‘.tcl’ if a file extension is not supplied.

Examples:

Example 1

The following example exports a Tcl script named “recreate.tcl” for the test project:-

Start Vivado in tcl mode and execute following commands:
% open_project test/test.xpr
% write_project_tcl recreate.tcl
% close_project

Example 2

The following example exports a Tcl script named “recreate.tcl” for the test project in the “./script” directory and specifies the “/tmp/test” directory path in the “create_project” command. When the “recreate.tcl” script is sourced in the Vivado Tcl shell, the project will be re-created in “/tmp/test” directory:-

Start Vivado in tcl mode and execute following commands:
% open_project test/test.xpr
% write_project_tcl -target_proj_dir “/tmp/test” ./script/recreate.tcl
% close_project
% source script/recreate.tcl

Example 3

The following Tcl commands exports Tcl script for the current project and writes all the properties, both default or non-default values:-

% write_project_tcl -all_properties recreate.tcl

Example 4

The following Tcl commands exports Tcl script for the current project and adds files that are local in this project. The recreated project will reference these files:-

% write_project_tcl -no_copy_sources recreate.tcl

Example 5

The following Tcl and shell commands opens a test project, exports “recreate.tcl” script for the current project in the current working directory, creates a new project in ./my_test directory, prints the list of files in the new project, prints the current project settings and then closes the newly created project:-

Start Vivado in tcl mode and execute following commands:
% open_project test/test.xpr
% write_project_tcl -force recreate.tcl
% close_project
% exit

From OS shell:

mkdir my_test
cd my_test
vivado -mode batch -source ../recreate.tcl -tclargs --origin_dir ..

Start Vivado in tcl mode and execute following commands:
% open_project test/test.xpr
% get_files -of_objects [get_filesets sources_1]
% report_property [current_project]
% close_project

Example 6

The following Tcl commands creates a new project named bft_test, adds files to the project, sets the fileset property, exports a tcl script named “bft.tcl” in the current working directory, creates a new project in “./my_bft” directory, prints the list of files in the new project (test_1.v and test_2.v), prints the “verilog_define” property value and then closes the newly created project:-

Start Vivado in tcl mode and execute following commands:
% create_project bft_test ./bft_test
% add_files test_1.v
% add_files test_2.v
% set_property verilog_define {a=10} [get_filesets sources_1]
% write_project_tcl -force bft.tcl
% close_project
% exit

From OS shell:

mkdir my_bft
cd my_bft
vivado -mode batch -source ../bft.tcl -tclargs --origin_dir ..

Start Vivado in tcl mode and execute following commands:
% open_project bft_test/bft_test.xpr
% get_files -of_objects [get_filesets sources_1]
% get_property verilog_define [get_filesets sources_1]
% close_project

See Also:

  • add_files
  • archive_project
  • close_project
  • create_project
  • current_project
  • get_files
  • get_property
  • open_project
  • report_property
  • set_property
`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 2023/07/08 23:38:24 // Design Name: // Module Name: hmc830_ctrl // Project Name: // Target Devices: // Tool Versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module hmc830_ctrl( input wire clk, output wire rst_n_delay, output wire start_cfg_hmc830 ); //power on 2s start cfg hmc830 parameter TIME_2S = 32'd40; reg [15:0] delay_cnt = 16'd0; reg rst_n_delay_r = 1'b0; always @ (posedge clk) begin if(delay_cnt == 16'd1000) begin delay_cnt <= delay_cnt; rst_n_delay_r <= 1'b1; end else begin delay_cnt <= delay_cnt + 1'b1 ; rst_n_delay_r <= 1'b0; end end assign rst_n_delay = rst_n_delay_r; ////////////////////按键控制配置芯片的寄存器 ///按键消抖 // reg write_key_press; // reg [31:0] delay_cnt1 = 32'd0; // // // parameter T20MS = 32'd999_999; // // always @ (posedge sys_clk or negedge sys_rst_n) // begin // if(~sys_rst_n) // begin // delay_cnt1 <= 32'd0; // end // else if(write_key) // begin // delay_cnt1 <= 32'd0; // end // else if((~write_key) && (delay_cnt1 <= T20MS)) // begin // delay_cnt1 <= delay_cnt1 + 1'b1; // end // else // begin // delay_cnt1 <= delay_cnt1; // end // end // // always @ (posedge sys_clk or negedge sys_rst_n) // begin // if(~sys_rst_n) // begin // write_key_press <= 1'b0; // end // else if(delay_cnt1 == (T20MS - 2)) // begin // write_key_press <= 1'b1; // end // else // begin // write_key_press <= 1'b0; // end // end reg [31:0] delay_time_cnt = 32'd0; // 2s 10 000 000 reg start_cfg_hmc830_r = 1'b0; always @ (posedge clk) begin if(delay_time_cnt == TIME_2S) begin // delay_time_cnt <= delay_time_cnt; delay_time_cnt <= 32'd0; end else begin delay_time_cnt <= delay_time_cnt + 1'b1 ; end end always @ (posedge clk) begin if((delay_time_cnt >= (TIME_2S - 10)) && (delay_time_cnt <= (TIME_2S - 2))) begin start_cfg_hmc830_r <= 1'b1; end else begin start_cfg_hmc830_r <= 1'b0; end end assign start_cfg_hmc830 = start_cfg_hmc830_r; endmodule `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 2023/07/08 18:56:30 // Design Name: // Module Name: hmc830_top // Project Name: // Target Devices: // Tool Versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module hmc830_top( input wire clk, //100mhz input wire rst_n , output wire sck_spi, output wire sdi_spi, output wire sen_spi, output wire hmc830_cfg_done ); wire div_clk_out; wire rst_n_delay; wire start_cfg_hmc830; div_clk div_clk( . clk(clk), . div_clk(div_clk_out) ); hmc830_ctrl hmc830_ctrl( . clk(div_clk_out), . rst_n_delay(rst_n_delay), . start_cfg_hmc830(start_cfg_hmc830) ); hmc830 hmc830( . sck_spi(sck_spi), . sdi_spi(sdi_spi), . sen_spi(sen_spi), . done(hmc830_cfg_done), . start(start_cfg_hmc830), . clock(div_clk_out), . reset(rst_n_delay), . FREQ_DATA(250) ); endmodule module TEST_ONE_LED( input wire clk, output wire sck_spi, output wire sdi_spi, output wire sen_spi, output wire cen, input wire pll_sdo_locked, output wire test_locked_led ); assign cen = 1'b1 ; assign test_locked_led = ~pll_sdo_locked ; reg adc_clk_r = 1'b0; always @ (posedge clk) begin adc_clk_r <= ~adc_clk_r; end assign adc_clk = adc_clk_r ; test_dac test_dac( .clk(clk), .dac_clk(dac_clk), .dac_data(dac_data) ); wire rst_n; rst_gen rst_gen( . clk(clk), .rst_n(rst_n) ); wire pll_c0; wire pll_c1; wire pll_locked; // // my_pll my_pll( // inclk0(clk), // c0(pll_c0), // c1(pll_c1), // locked(pll_locked) // ); pll pll( .inclk0(clk), .c0(pll_c0), .c1(pll_c1), .locked(pll_locked) ); wire hmc830_cfg_done ; hmc830_top hmc830_top( . clk(pll_c1), //100mhz // . rst_n() , . sck_spi(sck_spi), . sdi_spi(sdi_spi), . sen_spi(sen_spi), .hmc830_cfg_done(hmc830_cfg_done) ); endmodule `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 21:04:47 12/13/2017 // Design Name: // Module Name: hmc833 // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module hmc830( output wire sck_spi, output wire sdi_spi, output reg sen_spi, output reg done, input start, input clock, input reset, input [14:0] FREQ_DATA ); /***************************************************************** 为方便计算N分频器的整数和小数部分,在除法运算中选择改变除数大小,不改变被除数大小 被除数都为FREQ_DATA 在输出频率为3000~6000时,vco频率为1500~3000,除数为3000~6000 除数为Fpd*2 {Fpd[4:0],1'b0} 在输出频率为1500~3000时,vco频率为1500~3000,除数为1500~3000 除数为Fpd 在输出频率为750~1500时,vco频率为1500~3000,除数为750~1500 除数为Fpd/2 {1'b0,Fpd[5:1]}; ******************************************************************/ reg [6:0] Fpd_Divisor; //计算N分频器值的除数 reg Fout_Double_fundament; //输出频率倍频器 0:倍频 1:直通 Vco_Reg03h[0] reg [5:0] Fout_div ; //输出频率分频器 Vco_Reg02h[5:0] wire [14:0] Nint; //N分频器整数部分值 Reg_03h 共19位,高位补0 wire [6:0] Nint_Remainder ; //N分频器整数部余数 wire [30:0] Nfarcdividend; //N分频器小数部分被除数 wire [30:0] Nfarc; //N分频器小数部分值 Reg_04h 只取24位 Nfarc[23:0] reg reckon_done; reg [6:0] reckonTime_cnt; // assign Nfarcdividend = {Nint_Remainder,24'h000000} ; // DIVI_Nfarc DIVI_Nfarc ( // .clk(clock), // input clk // .dividend(Nfarcdividend), // input [30 : 0] dividend // .divisor(Fpd_Divisor), // input [6 : 0] divisor // .quotient(Nfarc) // output [30 : 0] quotient // ); // DIVI_NINT DIVI_NINT ( // .clk(clock), // input clk // .dividend(FREQ_DATA), // input [14 : 0] dividend // .divisor(Fpd_Divisor), // input [6 : 0] divisor // .quotient(Nint), // output [14 : 0] quotient // .fractional(Nint_Remainder)); // output [6 : 0] fractional // parameter Fpd = 6'd50; //鉴相频率50MHz // parameter Fpd = 6'd125; //鉴相频率75MHz // Fout_Double_fundament // always@(negedge clock or negedge reset)begin // if(!reset)Fout_Double_fundament <= 1'b1; // else if(FREQ_DATA > 15'd3000) Fout_Double_fundament <= 1'b0; // else Fout_Double_fundament <= 1'b1; // end // Fout_div // always@(negedge clock or negedge reset)begin // if(!reset) Fout_div <= 6'b00_0001; // else if(FREQ_DATA<=15'd1500) Fout_div <= 6'b00_0010; // else Fout_div <= 6'b00_0001; // end // Fpd_Divisor // always@(negedge clock or negedge reset)begin // if(!reset) Fpd_Divisor <= {1'b0,Fpd}; // else if((FREQ_DATA <= 15'd6000)&&(FREQ_DATA > 15'd3000)) Fpd_Divisor <= {Fpd,1'b0}; // else if((FREQ_DATA <= 15'd3000)&&(FREQ_DATA > 15'd1500)) Fpd_Divisor <= {1'b0,Fpd}; // else if((FREQ_DATA <= 15'd1500)&&(FREQ_DATA > 15'd750)) Fpd_Divisor <= {2'b00,Fpd[5:1]}; // end parameter S_start = 3'h0, S_reckon = 3'h1, S_idle = 3'h2, S_wr = 3'h3, S_ini = 3'h4, S_done = 3'h5; reg [2:0] state,next_state; reg [4:0] bit_cnt; reg [4:0] reg_cnt; reg wr_en,load,wr_end,shift,clr_reg_cnt,reckon; reg [31:0] shift_reg; reg [31:0] reg_init; assign sck_spi = (sen_spi == 1'b1)?clock:1'b0; assign sdi_spi = shift_reg[31]; always@(negedge clock or negedge reset) if(!reset)state <= S_start; else state <= next_state; always@(state or start or bit_cnt or reg_cnt or reckon_done)begin wr_en = 0; load = 0; wr_end = 0; shift = 0; clr_reg_cnt = 0; done = 0; reckon = 0; next_state = state; case(state) S_start: begin if(start == 1'b1) next_state = S_reckon; end S_reckon: begin reckon = 1'b1; if(reckon_done == 1'b1) next_state = S_idle; end S_idle: begin wr_en = 1'b1; load = 1'b1; next_state = S_wr; end S_wr: begin if(bit_cnt == 5'd31)begin wr_end = 1'b1; next_state = S_ini; end else shift = 1'b1; end S_ini: begin if(reg_cnt == 5'd21)begin clr_reg_cnt = 1'b1; next_state = S_done; end else begin wr_en = 1'b1; load = 1'b1; next_state = S_wr; end end S_done: begin // next_state = S_start; //// next_state = next_state; done = 1; end default: next_state = S_start; endcase end //sen_spi always@(negedge clock or negedge reset) if(!reset)sen_spi <= 1'b0; else if(wr_en == 1'b1)sen_spi <= 1'b1; else if(wr_end == 1'b1)sen_spi <= 1'b0; //shift_reg always@(negedge clock or negedge reset) if(!reset)shift_reg <= 32'h0; else if(load == 1'b1)shift_reg <= reg_init; else if(shift == 1'b1)shift_reg <= {shift_reg[30:0],1'b0}; //bit_cnt always@(negedge clock or negedge reset) if(!reset)bit_cnt <= 5'h0; else if(bit_cnt == 5'd31)bit_cnt <= 5'h0; else if(shift == 1'b1)bit_cnt <= bit_cnt + 1'b1; //reg_cnt always@(negedge clock or negedge reset) if(!reset)reg_cnt <= 5'h0; else if(clr_reg_cnt == 1'b1)reg_cnt <= 5'h0; else if(load == 1'b1)reg_cnt <= reg_cnt + 1'b1; // reckonTime_cnt reckon_done always@(negedge clock or negedge reset)begin if(!reset)begin reckonTime_cnt <= 7'd0; reckon_done <= 1'b0; end else if(reckonTime_cnt == 7'd70)begin reckonTime_cnt <= 7'd0; reckon_done <= 1'b1; end else if(reckon == 1'b1)begin reckonTime_cnt <= reckonTime_cnt +1'b1; reckon_done <= reckon_done; end else begin reckonTime_cnt <= 7'd0; reckon_done <= 1'b0; end end always@(reg_cnt or Nint or Fout_div or Nfarc or Fout_Double_fundament)begin case(reg_cnt) 5'd0: reg_init = {1'b0,6'h0,24'h00_00_20,1'b0}; 5'd1: reg_init = {1'b0,6'h0,24'h00_00_20,1'b0}; 5'd2: reg_init = {1'b0,6'h0,24'h00_00_00,1'b0}; 5'd3: reg_init = {1'b0,6'h0,24'h00_00_00,1'b0}; 5'd4: reg_init = {1'b0,6'h1,24'h00_00_02,1'b0}; 5'd5: reg_init = {1'b0,6'h2,24'h00_00_01,1'b0}; //REF DIVIDER R = 2 // 5'd6: reg_init = {1'b0,6'h5,8'h00,3'b111,Fout_div,4'h2,3'b000,1'b0}; //output div vaule Fout_div 射频输出的分频 5'd6: reg_init = {1'b0,6'h5,8'h00,3'b111,6'd24,4'h2,3'b000,1'b0}; //output div vaule Fout_div 射频输出的分频 5'd7: reg_init = {1'b0,6'hb,24'h07_c0_21,1'b0}; 5'd8: reg_init = {1'b0,6'hc,24'h00_00_00,1'b0}; 5'd9: reg_init = {1'b0,6'hf,24'h00_00_81,1'b0}; 5'd10: reg_init = {1'b0,6'h5,9'h000,4'h0,2'h0,1'h0,1'b0,4'h3,3'b000,1'b0}; // output double x2 Fout_Double_fundament // 5'd10: reg_init = {1'b0,6'h5,24'h00_08_18,1'b0}; // output double x2 Fout_Double_fundament 5'd11: reg_init = {1'b0,6'h5,24'h00_16_28,1'b0}; // 24'h00_16_28 = 24'b0000_0000_0001_0110_0010_1000 datasheet default setting 5'd12: reg_init = {1'b0,6'h5,24'h00_60_a0,1'b0}; // 24'h00_60_a0 = 24'b0000_0000_0110_0000_1010_0000 datasheet default setting 5'd13: reg_init = {1'b0,6'h5,24'h00_00_00,1'b0}; 5'd14: reg_init = {1'b0,6'h9,24'h54_23_64,1'b0}; 5'd15: reg_init = {1'b0,6'h8,24'hc1_be_ff,1'b0}; 5'd16: reg_init = {1'b0,6'h7,24'h00_05_4d,1'b0}; 5'd17: reg_init = {1'b0,6'ha,24'h00_20_46,1'b0}; 5'd18: reg_init = {1'b0,6'h6,24'h23_0a_7c,1'b0}; // 5'd19: reg_init = {1'b0,6'h3,9'h000,Nint,1'b0}; // Reg 03h N_INT 60 Nint 5'd19: reg_init = {1'b0,6'h3,9'h000,15'd48,1'b0}; // Reg 03h N_INT 20 Nint min 16 // 5'd20: reg_init = {1'b0,6'h4,Nfarc[23:0],1'b0}; //Reg 04h 5'd20: reg_init = {1'b0,6'h4,24'd0,1'b0}; //Reg 04h default: reg_init = 32'h0000_0000; endcase end endmodule 为什么这个代码可以配置寄存器,而我上边的不行,难道是SPI的时序问题吗
12-25
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