Documentation/virtual/kvm/devices/mpic.txt

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Documentation/virtual/kvm/devices/mpic.txt的中文翻译

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MPIC interrupt controller
=========================

MPIC中断控制器（多处理器中断控制器，Multi-Processor Interrupt Controller）
=========================

Device types supported:
  KVM_DEV_TYPE_FSL_MPIC_20     Freescale MPIC v2.0
  KVM_DEV_TYPE_FSL_MPIC_42     Freescale MPIC v4.2

支持的设备类型：
  KVM_DEV_TYPE_FSL_MPIC_20 飞思卡尔 MPIC v2.0
  KVM_DEV_TYPE_FSL_MPIC_42 飞思卡尔 MPIC v4.2

Only one MPIC instance, of any type, may be instantiated.  The created
MPIC will act as the system interrupt controller, connecting to each
vcpu's interrupt inputs.

只有一个任意类型的MPIC实例，可被实例化。创建的
MPIC将作为系统的中断控制器，连接到每个
虚拟处理器的中断输入。

Groups:
  KVM_DEV_MPIC_GRP_MISC
  Attributes:
    KVM_DEV_MPIC_BASE_ADDR (rw, 64-bit)
      Base address of the 256 KiB MPIC register space.  Must be
      naturally aligned.  A value of zero disables the mapping.
      Reset value is zero.

组：
  KVM_DEV_MPIC_GRP_MISC
  属性：
    KVM_DEV_MPIC_BASE_ADDR （可读可写，64位）
      256 KiB空间的MPIC基地址寄存器。必须
      自然对齐。零值禁用映射。
      复位值是零。

  KVM_DEV_MPIC_GRP_REGISTER (rw, 32-bit)
    Access an MPIC register, as if the access were made from the guest.
    "attr" is the byte offset into the MPIC register space.  Accesses
    must be 4-byte aligned.

  KVM_DEV_MPIC_GRP_REGISTER （可读可写 ， 32位）
    访问一个MPIC寄存器，就像是由客人制成的访问。
    “ attr”为MPIC寄存器空间的字节偏移量。访问
    必须是4字节对齐的。

    MSIs may be signaled by using this attribute group to write
    to the relevant MSIIR.

    MSI可能通过使用此属性组作为信号标志写
    到相关的MSIIR寄存器中 。

  KVM_DEV_MPIC_GRP_IRQ_ACTIVE (rw, 32-bit)
    IRQ input line for each standard openpic source.  0 is inactive and 1
    is active, regardless of interrupt sense.

  KVM_DEV_MPIC_GRP_IRQ_ACTIVE （可读可写 ， 32位）
    每个标准开放式可编程中断控制器源都有中断请求输入线。不管中断识别，0是无效状态， 1
    处于活动状态。

    For edge-triggered interrupts:  Writing 1 is considered an activating
    edge, and writing 0 is ignored.  Reading returns 1 if a previously
    signaled edge has not been acknowledged, and 0 otherwise.

    对于边沿触发的中断：写1被认为是一个活动的
    边沿，写0将被忽略。如果以前的信号边缘并没有被承认，
    读操作将返回1，否则为0。

    "attr" is the IRQ number.  IRQ numbers for standard sources are the
    byte offset of the relevant IVPR from EIVPR0, divided by 32.

   “ attr”是中断请求号。标准源的中断请求号
     等于从EIVPR0到相关的IVPR字节偏移量，除以32。

IRQ Routing:

  The MPIC emulation supports IRQ routing. Only a single MPIC device can
  be instantiated. Once that device has been created, it's available as
  irqchip id 0.

中断请求路由选择：

  MPIC仿真器支持IRQ路由选择。只有一个MPIC设备
  可以被实例化。一旦该设备已被创建，它就作为
  IRQ Chip 编号 0 。

  This irqchip 0 has 256 interrupt pins, which expose the interrupts in
  the main array of interrupt sources (a.k.a. "SRC" interrupts).

  此irqchip 0有256个中断引脚，这显示中断
  在中断源的主阵列中（又名“ SRC”中断）。

  The numbering is the same as the MPIC device tree binding -- based on
  the register offset from the beginning of the sources array, without
  regard to any subdivisions in chip documentation such as "internal"
  or "external" interrupts.

  这编号与MPIC设备树中绑定的编号是相同的 - 建立在
  从源队列的开始到寄存器偏移的基础上，而不关于
  芯片文件编制中的任何分支，如“内部”
  或“外部”中断。

  Access to non-SRC interrupts is not implemented through IRQ routing mechanisms.
 
  访问非SRC中断是不能通过中断请求路由选择机制实现的。