head.s分析(2)：SYSCFG配置

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最新推荐文章于 2025-08-10 20:02:09 发布

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分类专栏： bf561-uclinux 文章标签： exception performance system insert events timer

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本文介绍如何在ADI BF561 DSP上配置和使用Cycle Counter进行性能统计。通过对SYSCFG寄存器的设置，启用64位周期计数器，并详细解释了CYCLES和CYCLES2寄存器的功能及读取方法。

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http://blog.youkuaiyun.com/lights_joy/

lights@hb165.com

本文适用于

ADI bf561 DSP

uclinux-2008r1.5-rc3 (移植到vdsp5)

Visual DSP++ 5.0(update 5)

欢迎转载，但请保留作者信息

/* Enable Cycle Counter and Nesting Of Interrupts */

#ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES

R0 = SYSCFG_SNEN;

#else

R0 = SYSCFG_SNEN | SYSCFG_CCEN;

#endif

SYSCFG = R0;

这几行代码用于设置SYSCFG的值，关于SYSCFG这个寄存器，vdsp文件这样说：

The System Configuration Register (SYSCFG) shown in Figure 4-3 controls the configuration of the processor

对于BF561而言，只有CCEN和SSSTEP两位有效，在这里将CCEN位设置为1，表示要启用64位的cycle counter。而对SNEN的置位将被忽略。

System Configuration Register

在启用了CCEN之后，CYCLES和CYCLES2两个寄存器将开始统计CCLK的个数。

下面是vdsp文档中对CYCLES和CYCLES2这两个寄存器的一个说明：

The cycle counter counts CCLK cycles while the program is executing. All cycles, including execution, wait state, interrupts, and events, are counted while the processor is in User or Supervisor mode, but the cycle counter stops counting in Emulator mode.

The cycle counter is 64 bits wide and increments every cycle. The count value is stored in two 32-bit registers, CYCLES and CYCLES2. The least significant 32 bits (LSBs) are stored in CYCLES. The most significant 32 bits (MSBs) are stored in CYCLES2.

Note: To ensure read coherency, first read CYCLES, then CYCLES2, and then CYCLES again, to detect if an overflow has occurred in the LSBs during the read operations.

In User mode, these two registers may be read, but not written. In Supervisor and Emulator modes, they are read/write registers.

To enable the cycle counters, set the CCEN bit in the SYSCFG register. The following example shows how to use the cycle counter:

R2 = 0;

CYCLES = R2;

CYCLES2 = R2;

R2 = SYSCFG;

BITSET(R2,1);

SYSCFG = R2;

/* Insert code to be benchmarked here. */

R2 = SYSCFG;

BITCLR(R2,1);

SYSCFG = R2;